1RDTSET(8) System Manager's Manual RDTSET(8)
2
6 rtdset - Task CPU affinity and Intel(R) Resource Director Technology
7 control tool
8
10 rdtset -t <feature=value;...cpu=cpulist>... -c <cpulist> [-I] (-p
11 <pidlist> | [-k] cmd [<args>...])
12 rdtset -r <cpulist> -t <feature=value;...cpu=cpulist>... -c <cpulist>
13 [-I] (-p <pidlist> | [-k] cmd [<args>...])
14 rdtset -r <cpulist> -c <cpulist> (-p <pidlist> | [-k] cmd [<args>...])
15 rdtset -r <cpulist> -t <feature=value;...cpu=cpulist>... [-I] -p
16 <pidlist>
17 rdtset -t <feature=value> -I [-c <cpulist>] (-p <pidlist> | [-k] cmd
18 [<args>...])
19
21 For more details on Intel(R) Resource Director Technology see
22 http://www.intel.com/content/www/us/en/architecture-and-technol‐
23 ogy/resource-director-technology.html
24 or https://github.com/01org/intel-cmt-cat/wiki
25 The rdtset tool provides support to set up the CAT (Cache Allocation
27 Technology) and MBA (Memory Bandwidth Allocation) capabilities for a
28 task and set its CPU affinity. Current Intel(R) RDT allocation opera‐
29 tions of the utility are based on controlling MSR registers (via
30 libpqos library). Class of service 0 (CLOS0) is assumed as default one.
31 In command mode, rdtset forks and one process executes the command.
32 Another process waits for the task to terminate and restores default
33 allocation state by assigning cpu's back to CLOS0. This behavior is
34 not in place in PID mode.
35
37 rdtset options are as follow:
38 -h, --help
40 Show help
41 -v, --verbose
43 Verbose mode
44 -I, --iface-os
46 Set the library to use the kernel implementation. If not set the
47 default implementation is to program the MSR's directly.
48 -t --rdt feature=value;...cpu=cpulist
50 Specify Intel(R) RDT configuration, single class configuration
51 per -t, multiple -t options allowed.
52 Accepted values for features:
53 2, l2 for level 2 cache
54 3, l3 for level 3 cache
55 m, mba for MBA
56 For example:
58 -t 'l3=0xf;cpu=1'
60 CPU 1 uses four L3 cache-ways (mask 0xf)
61 -t 'l3=0xf;cpu=2' -t 'l3=0xf0;cpu=3,4,5'
63 CPU 2 uses four L3 cache-ways (mask 0xf), CPUs 3-5 share four L3
64 cache-ways (mask 0xf0), L3 cache-ways used by CPU 2 and 3-4 are
65 non-overlapping
66 -t 'l3=0xf;cpu=0-2' -t 'l3=0xf0;cpu=3,4,5'
68 CPUs 0-2 share four L3 cache-ways (mask 0xf), CPUs 3-5 share
69 four L3 cache-ways (mask 0xf0), L3 cache-ways used by CPUs 0-2
70 and 3-5 are non-overlapping
71 -t 'l3=0xf,0xf0;cpu=1'
73 On CDP enabled system, CPU 1 uses four cache-ways for code (mask
74 0xf) and four cache-ways for data (mask 0xf0), data and code
75 cache-ways are non-overlapping
76 -t 'mba=70;cpu=0-2'
78 CPUs 0-2 can utilize up to 70% of available memory bandwidth
79 -t 'mba=50;l3=0xf;cpu=1'
81 CPU 1 uses four L3 (mask 0xf) cache-ways and can utilize up to
82 50% of available memory bandwidth
83 Example PID type allocation configuration (requires -I option):
85 -t 'l3=0xf'
87 Allocate four L3 (mask 0xf) cache-ways to specified PIDs (-p
88 option) or command
89 -t 'l3=0xf;cpu=1;l3=0x1'
91 CPU 1 uses four L3 (mask 0xf) cache-ways
92 Specified PIDs (-p option) or command uses one L3 (mask 0x1)
93 cache-way
94 -c <cpulist>, --cpu <cpulist>
97 Specify CPU affinity configuration, a numerical list of proces‐
98 sors. The numbers are separated by commas and may include
99 ranges. For example: 1-3,4,5.
100 -p <pidlist>, --pid <pidlist>
102 Operate on existing PIDs
103 -r <cpulist>, --reset <cpulist>
105 Reset allocation for CPUs (assign COS#0 to listed CPUs)
106 For example:
107 -r 0-5
109 Reset allocation for CPUs 0-5
110 -r 0-5 -t 'l3=0xf0;cpu=0-5' -c 0-5 -p $BASHPID
112 Reconfigure allocation for CPUs 0-5
113 In order to reconfigure allocation, it is needed to reset cur‐
114 rent configuration
115 -k, --sudokeep
118 Do not drop sudo elevated privileges
119
121 CAT and MBA are configured using Model Specific Registers (MSRs) to set
122 up the class of service masks and manage the association of the
123 cores/logical threads to a class of service. The rdtset software exe‐
124 cutes in user space, and access to the MSRs is obtained through a stan‐
125 dard Linux*/FreeBSD* interface. Under Linux, the virtual file system
126 structure /dev/cpu/CPUNUM/msr provides an interface to read and write
127 the MSRs, under FreeBSD it is /dev/cpuctlCPUNUM. The msr/cpuctl file
128 interface is protected and requires root privileges. The msr/cpuctl
129 driver might not be auto-loaded and on some modular kernels the driver
130 may need to be loaded manually:
131 Under Linux:
133 sudo modprobe msr
134 Under FreeBSD:
136 sudo kldload cpuctl
137 Interface enforcement:
139 If you require system wide interface enforcement you can do so by set‐
140 ting the "RDT_IFACE" environment variable.
141
143 msr(4)
144
146 rdtset was written by Wojciech Andralojc <woj‐
147 ciechx.andralojc@intel.com>, Tomasz Kantecki <tomasz.kan‐
148 tecki@intel.com>, Michal Aleksinski <michalx.aleksinski@intel.com>,
149 Marcel Cornu <marcel.d.cornu@intel.com>
150 This is free software; see the source for copying conditions. There is
152 NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
153 PURPOSE.
154 February 21, 2017 RDTSET(8)