perl-Verilog-Perl/Verilog::Verilog-Perl(3pm)

1Verilog-Perl(3)       User Contributed Perl Documentation      Verilog-Perl(3)
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NAME

6       Verilog-Perl - Overview of Verilog language packages for Perl
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DESCRIPTION

9       The Verilog-Perl distribution provides Perl parsing and utilities for
10       the Verilog Language.  This file provides an overview of the
11       distribution, for specific details on each component, see that
12       component's manpage.
13
14       You may also want to try the AUTO features present in
15       http://www.veripool.org/verilog-mode <http://www.veripool.org/verilog-
16       mode> Verilog-Mode.
17

INSTALLATION

19       Skip this section if Verilog-Perl has already been installed.
20
21   Supported Systems
22       Verilog-Perl should run on any system with Perl, G++, Flex, and Bison.
23       It is known to work on at least:
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25       ·   sparc-sun-solaris2.5.1
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27       ·   i386-linux
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29       ·   i686-w2k-cygwin
30
31   CPAN Installation
32           Easiest installation is using the "CPAN" command line that comes
33           with Perl.  After configuring CPAN the first time, simply
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35              $ cpan
36              cpan> install Verilog-Perl
37
38           Read the rest of this file for details on the programs provided.
39
40   Manual Installation
41           Download the latest version from <http://www.perl.org/CPAN/>, or
42           from http://www.veripool.org/verilog-perl
43           <http://www.veripool.org/verilog-perl>.
44
45           "cd" to the directory containing this README notice.
46
47           Type "perl Makefile.PL" to configure Verilog for your system.
48
49           Type "make" to compile Verilog.  Some Solaris users have had
50           trouble with "open" being redefined.  If this happens, try editing
51           the Makefile to change _FILE_OFFSET_BITS to 32 instead of 64.
52
53           Type "make test" to check the package.  If you don't have Synopsys'
54           VCS, the test will print a warning, which you can ignore.
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56           Type "make install" to install the programs and any data files and
57           documentation.
58
59           Read the rest of this file for details on the programs provided.
60

SCRIPTS

62       The following scripts are installed by Verilog-Perl:
63
64       vhier
65           Vhier reads the Verilog files passed on the command line and
66           outputs a tree of all of the filenames, modules, and cells
67           referenced by that file.
68
69       vpassert
70           Vpassert will read the specified Verilog files and preprocess
71           special PLI assertions.
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73       vppreproc
74           Vppreproc (Verilog-Perl Pre Processor) reads the Verilog files
75           passed on the command line and outputs preprocessed output.
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77       vrename
78           Vrename will allow a signal to be changed across all levels of the
79           design hierarchy, or to create a cross reference of signal names.
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PACKAGES

82       Verilog::Getopt
83           Verilog::Getopt provides standardized handling of options similar
84           to Verilog/VCS and cc/GCC.
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86       Verilog::Language
87           Verilog::Language provides general utilities for using the Verilog
88           Language, such as parsing numbers or determining what keywords
89           exist.
90
91       Verilog::Netlist
92           Verilog::Netlist reads and holds interconnect information about a
93           whole design database.
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95       Verilog::Netlist::Cell
96           A Verilog::Netlist::Cell object is created by Verilog::Netlist for
97           every instantiation in the current module.
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99       Verilog::Netlist::ContAssign
100           A Verilog::Netlist::ContAssign object is created by
101           Verilog::Netlist for every continuous assignment in the current
102           module.
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104       Verilog::Netlist::File
105           Verilog::Netlist::File allows Verilog::Netlist objects to be read
106           and written in Verilog format.
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108       Verilog::Netlist::Module
109           A Verilog::Netlist::Module object is created by Verilog::Netlist
110           for every module in the design.
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112       Verilog::Netlist::Net
113           A Verilog::Netlist::Net object is created by
114           Verilog::Netlist::Module for every signal and input/output
115           declaration in the current module.
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117       Verilog::Netlist::Pin
118           A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell
119           for for each pin connection on a cell.
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121       Verilog::Netlist::Port
122           A Verilog::Netlist::Port object is created by
123           Verilog::Netlist::Module for every port connection in the module.
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125       Verilog::Netlist::Subclas
126           The Verilog::Netlist::Subclass is used as a base class for all
127           Verilog::Netlist::* structures.
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129       Verilog::Parser
130           Verilog::Parser will tokenize a Verilog file and invoke various
131           callback methods.
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133       Verilog::Preproc
134           Verilog::Preproc reads Verilog files, and preprocesses them
135           according to the Verilog specification.  Programs can be easily
136           converted from reading a IO::File into reading preprocessed output
137           from Verilog::Preproc.
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139       Verilog::SigParse
140           Verilog::SigParser builds upon the Verilog::Parser package to
141           provide callbacks for when a signal is declared, a module
142           instantiated, or a module defined.
143

WHICH PARSER PACKAGE?

145       If you are starting a new application which needs to parse the Verilog
146       language you have several tools available to you.  Which you pick
147       depends on how low level and complete the information you need is.
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149       VParseBison.y
150           The low level VParse* source files may be of use when you need a
151           starting point for your own a full C++ SystemVerilog grammar
152           parser, using Bison and Flex.  It understands the full
153           SystemVerilog 2009 grammar (1800-2009 Appendix A).
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155       Verilog::Preproc
156           Verilog::Preproc is useful when you need only text out, or a list
157           of defines, etc.  It can preprocess a file, or be used to provide
158           the Verilog macro language on top of synthesis scripts.  It
159           understands the full SystemVerilog 2009 preprocessor syntax.
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161       Verilog::Parser
162           Verilog::Parser is useful when you need to tokenize or write source
163           filters (where you need everything including whitespace).  It can
164           take raw files, or preprocessed input.  It understands all
165           SystemVerilog 2005 keywords.
166
167       Abstract Syntax Tree
168           Verilog::Parser knows enough to make a complete Abstract Syntax
169           Tree (AST) of Verilog syntax, however this hasn't been implemented
170           yet.  This would allow any arbitrary transformation of Verilog
171           syntax (everthing is known excluding whitespace).  If you'd find
172           this useful please contact the author.
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174       Verilog::SigParser
175           Verilog::SigParser is useful when you need a list of modules,
176           signals, ports, functions, etc.  It requires a preprocessed file,
177           and can parse all SystemVerilog 2005 files, but only provides
178           callbacks on certain interesting things.
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180       Verilog::Netlist
181           Verilog::Netlist is useful for when you need the hierarchy, and a
182           list of signals per module, pins per cell, etc.  It builds upon the
183           output of Verilog::SigParser, so requires preprocessed files.  It
184           parses all SystemVerilog 2005 files, but not all SystemVerilog
185           constructs are loaded into objects.
186
187           This is probably the most popular choice.
188
189       VPI Using the VPI is the best way to access the behavior of the design.
190           It is not part of this package as it requires a compliant simulator
191           and C++ code to call the VPI, and understands as much of the
192           language as the simulator supports.  This allows writing lint
193           checks and full knowledge of all parts of the code, but generally
194           requires the most work (short of writing a parser from scratch.)
195
196       Verilator
197           The Verilator program also contains a very similar front end as
198           Verilog-Perl.  It also understands how to elaborate and connect
199           complex pins and types.  If you're looking to add some lint like
200           checks against netlists, this may be a better starting point.
201
202       Verilog-Mode for Emacs
203           Although not a parser, a common requested use of Verilog-Perl is to
204           automatically make shell modules and interconnect modules.
205           Verilog-Mode is a better solution to this problem, as it results in
206           completely portable code; the program (Verilog-Mode) isn't needed
207           for others to update the design.  It's also in very common usage,
208           including by many IP providers.
209

FAQ

211       Why do I get "unexpected `do'" or "unexpected `bit'" errors?
212           Do, bit, ref, return, and other words are now SystemVerilog
213           keywords.  You should change your code to not use them to insure it
214           works with newer tools.  Alternatively, surround them by the
215           Verilog 2005/SystemVerilog begin_keywords pragma to indicate
216           Verilog 2001 code.
217
218              `begin_keywords "1364-2001"
219                 integer bit; initial bit = 1;
220              `end_keywords
221
222           Alternatively use the --language (for vhier) or
223           Verilog::Language::language_standard call to specify "1364-2001",
224           or for really old code, "1364-1995".
225
226           But, again, you really should fix the Verilog code.
227

DISTRIBUTION

229       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
230       software tool suite.  The latest version is available from CPAN and
231       from http://www.veripool.org/verilog-perl
232       <http://www.veripool.org/verilog-perl>.
233
234       Copyright 2000-2010 by Wilson Snyder.  This package is free software;
235       you can redistribute it and/or modify it under the terms of either the
236       GNU Lesser General Public License Version 3 or the Perl Artistic
237       License Version 2.0.
238
239       This code is provided with no warranty of any kind, and is used
240       entirely at your own risk.
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AUTHORS

243       Wilson Snyder <wsnyder@wsnyder.org>
244