1AS(1)                        GNU Development Tools                       AS(1)
2
3
4

NAME

6       AS - the portable GNU assembler.
7

SYNOPSIS

9       as [-a[cdghlns][=file]] [--alternate] [-D]
10        [--compress-debug-sections]  [--nocompress-debug-sections]
11        [--debug-prefix-map old=new]
12        [--defsym sym=val] [-f] [-g] [--gstabs]
13        [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14        [--help] [-I dir] [-J]
15        [-K] [-L] [--listing-lhs-width=NUM]
16        [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
17        [--listing-cont-lines=NUM] [--keep-locals]
18        [--no-pad-sections]
19        [-o objfile] [-R]
20        [--hash-size=NUM] [--reduce-memory-overheads]
21        [--statistics]
22        [-v] [-version] [--version]
23        [-W] [--warn] [--fatal-warnings] [-w] [-x]
24        [-Z] [@FILE]
25        [--sectname-subst] [--size-check=[error|warning]]
26        [--elf-stt-common=[no|yes]]
27        [--generate-missing-build-notes=[no|yes]]
28        [--target-help] [target-options]
29        [--|files ...]
30

TARGET

32       Target AArch64 options:
33          [-EB|-EL]
34          [-mabi=ABI]
35
36       Target Alpha options:
37          [-mcpu]
38          [-mdebug | -no-mdebug]
39          [-replace | -noreplace]
40          [-relax] [-g] [-Gsize]
41          [-F] [-32addr]
42
43       Target ARC options:
44          [-mcpu=cpu]
45          [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
46          [-mcode-density]
47          [-mrelax]
48          [-EB|-EL]
49
50       Target ARM options:
51          [-mcpu=processor[+extension...]]
52          [-march=architecture[+extension...]]
53          [-mfpu=floating-point-format]
54          [-mfloat-abi=abi]
55          [-meabi=ver]
56          [-mthumb]
57          [-EB|-EL]
58          [-mapcs-32|-mapcs-26|-mapcs-float|
59           -mapcs-reentrant]
60          [-mthumb-interwork] [-k]
61
62       Target Blackfin options:
63          [-mcpu=processor[-sirevision]]
64          [-mfdpic]
65          [-mno-fdpic]
66          [-mnopic]
67
68       Target CRIS options:
69          [--underscore | --no-underscore]
70          [--pic] [-N]
71          [--emulation=criself | --emulation=crisaout]
72          [--march=v0_v10 | --march=v10 | --march=v32 |
73       --march=common_v10_v32]
74
75       Target D10V options:
76          [-O]
77
78       Target D30V options:
79          [-O|-n|-N]
80
81       Target EPIPHANY options:
82          [-mepiphany|-mepiphany16]
83
84       Target H8/300 options:
85          [-h-tick-hex]
86
87       Target i386 options:
88          [--32|--x32|--64] [-n]
89          [-march=CPU[+EXTENSION...]] [-mtune=CPU]
90
91       Target i960 options:
92          [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
93           -AKC|-AMC]
94          [-b] [-no-relax]
95
96       Target IA-64 options:
97          [-mconstant-gp|-mauto-pic]
98          [-milp32|-milp64|-mlp64|-mp64]
99          [-mle|mbe]
100          [-mtune=itanium1|-mtune=itanium2]
101          [-munwind-check=warning|-munwind-check=error]
102          [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
103          [-x|-xexplicit] [-xauto] [-xdebug]
104
105       Target IP2K options:
106          [-mip2022|-mip2022ext]
107
108       Target M32C options:
109          [-m32c|-m16c] [-relax] [-h-tick-hex]
110
111       Target M32R options:
112          [--m32rx|--[no-]warn-explicit-parallel-conflicts|
113          --W[n]p]
114
115       Target M680X0 options:
116          [-l] [-m68000|-m68010|-m68020|...]
117
118       Target M68HC11 options:
119          [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
120          [-mshort|-mlong]
121          [-mshort-double|-mlong-double]
122          [--force-long-branches] [--short-branches]
123          [--strict-direct-mode] [--print-insn-syntax]
124          [--print-opcodes] [--generate-example]
125
126       Target MCORE options:
127          [-jsri2bsr] [-sifilter] [-relax]
128          [-mcpu=[210|340]]
129
130       Target Meta options:
131          [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
132
133       Target MIPS options:
134          [-nocpp] [-EL] [-EB] [-O[optimization level]]
135          [-g[debug level]] [-G num] [-KPIC] [-call_shared]
136          [-non_shared] [-xgot [-mvxworks-pic]
137          [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
138          [-mfp64] [-mgp64] [-mfpxx]
139          [-modd-spreg] [-mno-odd-spreg]
140          [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
141          [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
142          [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
143          [-mips64r3] [-mips64r5] [-mips64r6]
144          [-construct-floats] [-no-construct-floats]
145          [-mignore-branch-isa] [-mno-ignore-branch-isa]
146          [-mnan=encoding]
147          [-trap] [-no-break] [-break] [-no-trap]
148          [-mips16] [-no-mips16]
149          [-mmips16e2] [-mno-mips16e2]
150          [-mmicromips] [-mno-micromips]
151          [-msmartmips] [-mno-smartmips]
152          [-mips3d] [-no-mips3d]
153          [-mdmx] [-no-mdmx]
154          [-mdsp] [-mno-dsp]
155          [-mdspr2] [-mno-dspr2]
156          [-mdspr3] [-mno-dspr3]
157          [-mmsa] [-mno-msa]
158          [-mxpa] [-mno-xpa]
159          [-mmt] [-mno-mt]
160          [-mmcu] [-mno-mcu]
161          [-minsn32] [-mno-insn32]
162          [-mfix7000] [-mno-fix7000]
163          [-mfix-rm7000] [-mno-fix-rm7000]
164          [-mfix-vr4120] [-mno-fix-vr4120]
165          [-mfix-vr4130] [-mno-fix-vr4130]
166          [-mdebug] [-no-mdebug]
167          [-mpdr] [-mno-pdr]
168
169       Target MMIX options:
170          [--fixed-special-register-names] [--globalize-symbols]
171          [--gnu-syntax] [--relax] [--no-predefined-symbols]
172          [--no-expand] [--no-merge-gregs] [-x]
173          [--linker-allocated-gregs]
174
175       Target Nios II options:
176          [-relax-all] [-relax-section] [-no-relax]
177          [-EB] [-EL]
178
179       Target NDS32 options:
180           [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
181           [-misa=isa] [-mabi=abi] [-mall-ext]
182           [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
183           [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
184           [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
185           [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
186           [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
187           [-mb2bb]
188
189       Target PDP11 options:
190          [-mpic|-mno-pic] [-mall] [-mno-extensions]
191          [-mextension|-mno-extension]
192          [-mcpu] [-mmachine]
193
194       Target picoJava options:
195          [-mb|-me]
196
197       Target PowerPC options:
198          [-a32|-a64]
199          [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
200           -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
201           -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
202           -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
203           -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
204           -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
205          [-many] [-maltivec|-mvsx|-mhtm|-mvle]
206          [-mregnames|-mno-regnames]
207          [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
208          [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
209          [-msolaris|-mno-solaris]
210          [-nops=count]
211
212       Target PRU options:
213          [-link-relax]
214          [-mnolink-relax]
215          [-mno-warn-regname-label]
216
217       Target RISC-V options:
218          [-fpic|-fPIC|-fno-pic]
219          [-march=ISA]
220          [-mabi=ABI]
221
222       Target RL78 options:
223          [-mg10]
224          [-m32bit-doubles|-m64bit-doubles]
225
226       Target RX options:
227          [-mlittle-endian|-mbig-endian]
228          [-m32bit-doubles|-m64bit-doubles]
229          [-muse-conventional-section-names]
230          [-msmall-data-limit]
231          [-mpid]
232          [-mrelax]
233          [-mint-register=number]
234          [-mgcc-abi|-mrx-abi]
235
236       Target s390 options:
237          [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
238          [-mregnames|-mno-regnames]
239          [-mwarn-areg-zero]
240
241       Target SCORE options:
242          [-EB][-EL][-FIXDD][-NWARN]
243          [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
244          [-march=score7][-march=score3]
245          [-USE_R1][-KPIC][-O0][-G num][-V]
246
247       Target SPARC options:
248          [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
249           -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
250           -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
251           -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
252           -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
253           -Asparcvisr|-Asparc5]
254          [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
255           -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
256           -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
257           -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
258           -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
259           -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
260           -bump]
261          [-32|-64]
262          [--enforce-aligned-data][--dcti-couples-detect]
263
264       Target TIC54X options:
265        [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
266        [-merrors-to-file <filename>|-me <filename>]
267
268       Target TIC6X options:
269          [-march=arch] [-mbig-endian|-mlittle-endian]
270          [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
271          [-mpic|-mno-pic]
272
273       Target TILE-Gx options:
274          [-m32|-m64][-EB][-EL]
275
276       Target Visium options:
277          [-mtune=arch]
278
279       Target Xtensa options:
280        [--[no-]text-section-literals] [--[no-]auto-litpools]
281        [--[no-]absolute-literals]
282        [--[no-]target-align] [--[no-]longcalls]
283        [--[no-]transform]
284        [--rename-section oldname=newname]
285        [--[no-]trampolines]
286
287       Target Z80 options:
288         [-z80] [-r800]
289         [ -ignore-undocumented-instructions] [-Wnud]
290         [ -ignore-unportable-instructions] [-Wnup]
291         [ -warn-undocumented-instructions] [-Wud]
292         [ -warn-unportable-instructions] [-Wup]
293         [ -forbid-undocumented-instructions] [-Fud]
294         [ -forbid-unportable-instructions] [-Fup]
295

DESCRIPTION

297       GNU as is really a family of assemblers.  If you use (or have used) the
298       GNU assembler on one architecture, you should find a fairly similar
299       environment when you use it on another architecture.  Each version has
300       much in common with the others, including object file formats, most
301       assembler directives (often called pseudo-ops) and assembler syntax.
302
303       as is primarily intended to assemble the output of the GNU C compiler
304       "gcc" for use by the linker "ld".  Nevertheless, we've tried to make as
305       assemble correctly everything that other assemblers for the same
306       machine would assemble.  Any exceptions are documented explicitly.
307       This doesn't mean as always uses the same syntax as another assembler
308       for the same architecture; for example, we know of several incompatible
309       versions of 680x0 assembly language syntax.
310
311       Each time you run as it assembles exactly one source program.  The
312       source program is made up of one or more files.  (The standard input is
313       also a file.)
314
315       You give as a command line that has zero or more input file names.  The
316       input files are read (from left file name to right).  A command line
317       argument (in any position) that has no special meaning is taken to be
318       an input file name.
319
320       If you give as no file names it attempts to read one input file from
321       the as standard input, which is normally your terminal.  You may have
322       to type ctl-D to tell as there is no more program to assemble.
323
324       Use -- if you need to explicitly name the standard input file in your
325       command line.
326
327       If the source is empty, as produces a small, empty object file.
328
329       as may write warnings and error messages to the standard error file
330       (usually your terminal).  This should not happen when  a compiler runs
331       as automatically.  Warnings report an assumption made so that as could
332       keep assembling a flawed program; errors report a grave problem that
333       stops the assembly.
334
335       If you are invoking as via the GNU C compiler, you can use the -Wa
336       option to pass arguments through to the assembler.  The assembler
337       arguments must be separated from each other (and the -Wa) by commas.
338       For example:
339
340               gcc -c -g -O -Wa,-alh,-L file.c
341
342       This passes two options to the assembler: -alh (emit a listing to
343       standard output with high-level and assembly source) and -L (retain
344       local symbols in the symbol table).
345
346       Usually you do not need to use this -Wa mechanism, since many compiler
347       command-line options are automatically passed to the assembler by the
348       compiler.  (You can call the GNU compiler driver with the -v option to
349       see precisely what options it passes to each compilation pass,
350       including the assembler.)
351

OPTIONS

353       @file
354           Read command-line options from file.  The options read are inserted
355           in place of the original @file option.  If file does not exist, or
356           cannot be read, then the option will be treated literally, and not
357           removed.
358
359           Options in file are separated by whitespace.  A whitespace
360           character may be included in an option by surrounding the entire
361           option in either single or double quotes.  Any character (including
362           a backslash) may be included by prefixing the character to be
363           included with a backslash.  The file may itself contain additional
364           @file options; any such options will be processed recursively.
365
366       -a[cdghlmns]
367           Turn on listings, in any of a variety of ways:
368
369           -ac omit false conditionals
370
371           -ad omit debugging directives
372
373           -ag include general information, like as version and options passed
374
375           -ah include high-level source
376
377           -al include assembly
378
379           -am include macro expansions
380
381           -an omit forms processing
382
383           -as include symbols
384
385           =file
386               set the name of the listing file
387
388           You may combine these options; for example, use -aln for assembly
389           listing without forms processing.  The =file option, if used, must
390           be the last one.  By itself, -a defaults to -ahls.
391
392       --alternate
393           Begin in alternate macro mode.
394
395       --compress-debug-sections
396           Compress DWARF debug sections using zlib with SHF_COMPRESSED from
397           the ELF ABI.  The resulting object file may not be compatible with
398           older linkers and object file utilities.  Note if compression would
399           make a given section larger then it is not compressed.
400
401       --compress-debug-sections=none
402       --compress-debug-sections=zlib
403       --compress-debug-sections=zlib-gnu
404       --compress-debug-sections=zlib-gabi
405           These options control how DWARF debug sections are compressed.
406           --compress-debug-sections=none is equivalent to
407           --nocompress-debug-sections.  --compress-debug-sections=zlib and
408           --compress-debug-sections=zlib-gabi are equivalent to
409           --compress-debug-sections.  --compress-debug-sections=zlib-gnu
410           compresses DWARF debug sections using zlib.  The debug sections are
411           renamed to begin with .zdebug.  Note if compression would make a
412           given section larger then it is not compressed nor renamed.
413
414       --nocompress-debug-sections
415           Do not compress DWARF debug sections.  This is usually the default
416           for all targets except the x86/x86_64, but a configure time option
417           can be used to override this.
418
419       -D  Ignored.  This option is accepted for script compatibility with
420           calls to other assemblers.
421
422       --debug-prefix-map old=new
423           When assembling files in directory old, record debugging
424           information describing them as in new instead.
425
426       --defsym sym=value
427           Define the symbol sym to be value before assembling the input file.
428           value must be an integer constant.  As in C, a leading 0x indicates
429           a hexadecimal value, and a leading 0 indicates an octal value.  The
430           value of the symbol can be overridden inside a source file via the
431           use of a ".set" pseudo-op.
432
433       -f  "fast"---skip whitespace and comment preprocessing (assume source
434           is compiler output).
435
436       -g
437       --gen-debug
438           Generate debugging information for each assembler source line using
439           whichever debug format is preferred by the target.  This currently
440           means either STABS, ECOFF or DWARF2.
441
442       --gstabs
443           Generate stabs debugging information for each assembler line.  This
444           may help debugging assembler code, if the debugger can handle it.
445
446       --gstabs+
447           Generate stabs debugging information for each assembler line, with
448           GNU extensions that probably only gdb can handle, and that could
449           make other debuggers crash or refuse to read your program.  This
450           may help debugging assembler code.  Currently the only GNU
451           extension is the location of the current working directory at
452           assembling time.
453
454       --gdwarf-2
455           Generate DWARF2 debugging information for each assembler line.
456           This may help debugging assembler code, if the debugger can handle
457           it.  Note---this option is only supported by some targets, not all
458           of them.
459
460       --gdwarf-sections
461           Instead of creating a .debug_line section, create a series of
462           .debug_line.foo sections where foo is the name of the corresponding
463           code section.  For example a code section called .text.func will
464           have its dwarf line number information placed into a section called
465           .debug_line.text.func.  If the code section is just called .text
466           then debug line section will still be called just .debug_line
467           without any suffix.
468
469       --size-check=error
470       --size-check=warning
471           Issue an error or warning for invalid ELF .size directive.
472
473       --elf-stt-common=no
474       --elf-stt-common=yes
475           These options control whether the ELF assembler should generate
476           common symbols with the "STT_COMMON" type.  The default can be
477           controlled by a configure option --enable-elf-stt-common.
478
479       --generate-missing-build-notes=yes
480       --generate-missing-build-notes=no
481           These options control whether the ELF assembler should generate GNU
482           Build attribute notes if none are present in the input sources.
483           The default can be controlled by the --enable-generate-build-notes
484           configure option.
485
486       --help
487           Print a summary of the command line options and exit.
488
489       --target-help
490           Print a summary of all target specific options and exit.
491
492       -I dir
493           Add directory dir to the search list for ".include" directives.
494
495       -J  Don't warn about signed overflow.
496
497       -K  Issue warnings when difference tables altered for long
498           displacements.
499
500       -L
501       --keep-locals
502           Keep (in the symbol table) local symbols.  These symbols start with
503           system-specific local label prefixes, typically .L for ELF systems
504           or L for traditional a.out systems.
505
506       --listing-lhs-width=number
507           Set the maximum width, in words, of the output data column for an
508           assembler listing to number.
509
510       --listing-lhs-width2=number
511           Set the maximum width, in words, of the output data column for
512           continuation lines in an assembler listing to number.
513
514       --listing-rhs-width=number
515           Set the maximum width of an input source line, as displayed in a
516           listing, to number bytes.
517
518       --listing-cont-lines=number
519           Set the maximum number of lines printed in a listing for a single
520           line of input to number + 1.
521
522       --no-pad-sections
523           Stop the assembler for padding the ends of output sections to the
524           alignment of that section.  The default is to pad the sections, but
525           this can waste space which might be needed on targets which have
526           tight memory constraints.
527
528       -o objfile
529           Name the object-file output from as objfile.
530
531       -R  Fold the data section into the text section.
532
533       --hash-size=number
534           Set the default size of GAS's hash tables to a prime number close
535           to number.  Increasing this value can reduce the length of time it
536           takes the assembler to perform its tasks, at the expense of
537           increasing the assembler's memory requirements.  Similarly reducing
538           this value can reduce the memory requirements at the expense of
539           speed.
540
541       --reduce-memory-overheads
542           This option reduces GAS's memory requirements, at the expense of
543           making the assembly processes slower.  Currently this switch is a
544           synonym for --hash-size=4051, but in the future it may have other
545           effects as well.
546
547       --sectname-subst
548           Honor substitution sequences in section names.
549
550       --statistics
551           Print the maximum space (in bytes) and total time (in seconds) used
552           by assembly.
553
554       --strip-local-absolute
555           Remove local absolute symbols from the outgoing symbol table.
556
557       -v
558       -version
559           Print the as version.
560
561       --version
562           Print the as version and exit.
563
564       -W
565       --no-warn
566           Suppress warning messages.
567
568       --fatal-warnings
569           Treat warnings as errors.
570
571       --warn
572           Don't suppress warning messages or treat them as errors.
573
574       -w  Ignored.
575
576       -x  Ignored.
577
578       -Z  Generate an object file even after errors.
579
580       -- | files ...
581           Standard input, or source files to assemble.
582
583       The following options are available when as is configured for the
584       64-bit mode of the ARM Architecture (AArch64).
585
586       -EB This option specifies that the output generated by the assembler
587           should be marked as being encoded for a big-endian processor.
588
589       -EL This option specifies that the output generated by the assembler
590           should be marked as being encoded for a little-endian processor.
591
592       -mabi=abi
593           Specify which ABI the source code uses.  The recognized arguments
594           are: "ilp32" and "lp64", which decides the generated object file in
595           ELF32 and ELF64 format respectively.  The default is "lp64".
596
597       -mcpu=processor[+extension...]
598           This option specifies the target processor.  The assembler will
599           issue an error message if an attempt is made to assemble an
600           instruction which will not execute on the target processor.  The
601           following processor names are recognized: "cortex-a35",
602           "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a72",
603           "cortex-a73", "cortex-a75", "exynos-m1", "falkor", "qdf24xx",
604           "saphira", "thunderx", "vulcan", "xgene1" and "xgene2".  The
605           special name "all" may be used to allow the assembler to accept
606           instructions valid for any supported processor, including all
607           optional extensions.
608
609           In addition to the basic instruction set, the assembler can be told
610           to accept, or restrict, various extension mnemonics that extend the
611           processor.
612
613           If some implementations of a particular processor can have an
614           extension, then then those extensions are automatically enabled.
615           Consequently, you will not normally have to specify any additional
616           extensions.
617
618       -march=architecture[+extension...]
619           This option specifies the target architecture.  The assembler will
620           issue an error message if an attempt is made to assemble an
621           instruction which will not execute on the target architecture.  The
622           following architecture names are recognized: "armv8-a",
623           "armv8.1-a", "armv8.2-a", "armv8.3-a" and "armv8.4-a".
624
625           If both -mcpu and -march are specified, the assembler will use the
626           setting for -mcpu.  If neither are specified, the assembler will
627           default to -mcpu=all.
628
629           The architecture option can be extended with the same instruction
630           set extension options as the -mcpu option.  Unlike -mcpu,
631           extensions are not always enabled by default,
632
633       -mverbose-error
634           This option enables verbose error messages for AArch64 gas.  This
635           option is enabled by default.
636
637       -mno-verbose-error
638           This option disables verbose error messages in AArch64 gas.
639
640       The following options are available when as is configured for an Alpha
641       processor.
642
643       -mcpu
644           This option specifies the target processor.  If an attempt is made
645           to assemble an instruction which will not execute on the target
646           processor, the assembler may either expand the instruction as a
647           macro or issue an error message.  This option is equivalent to the
648           ".arch" directive.
649
650           The following processor names are recognized: 21064, "21064a",
651           21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
652           "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
653           "ev67", "ev68".  The special name "all" may be used to allow the
654           assembler to accept instructions valid for any Alpha processor.
655
656           In order to support existing practice in OSF/1 with respect to
657           ".arch", and existing practice within MILO (the Linux ARC
658           bootloader), the numbered processor names (e.g. 21064) enable the
659           processor-specific PALcode instructions, while the "electro-vlasic"
660           names (e.g. "ev4") do not.
661
662       -mdebug
663       -no-mdebug
664           Enables or disables the generation of ".mdebug" encapsulation for
665           stabs directives and procedure descriptors.  The default is to
666           automatically enable ".mdebug" when the first stabs directive is
667           seen.
668
669       -relax
670           This option forces all relocations to be put into the object file,
671           instead of saving space and resolving some relocations at assembly
672           time.  Note that this option does not propagate all symbol
673           arithmetic into the object file, because not all symbol arithmetic
674           can be represented.  However, the option can still be useful in
675           specific applications.
676
677       -replace
678       -noreplace
679           Enables or disables the optimization of procedure calls, both at
680           assemblage and at link time.  These options are only available for
681           VMS targets and "-replace" is the default.  See section 1.4.1 of
682           the OpenVMS Linker Utility Manual.
683
684       -g  This option is used when the compiler generates debug information.
685           When gcc is using mips-tfile to generate debug information for
686           ECOFF, local labels must be passed through to the object file.
687           Otherwise this option has no effect.
688
689       -Gsize
690           A local common symbol larger than size is placed in ".bss", while
691           smaller symbols are placed in ".sbss".
692
693       -F
694       -32addr
695           These options are ignored for backward compatibility.
696
697       The following options are available when as is configured for an ARC
698       processor.
699
700       -mcpu=cpu
701           This option selects the core processor variant.
702
703       -EB | -EL
704           Select either big-endian (-EB) or little-endian (-EL) output.
705
706       -mcode-density
707           Enable Code Density extenssion instructions.
708
709       The following options are available when as is configured for the ARM
710       processor family.
711
712       -mcpu=processor[+extension...]
713           Specify which ARM processor variant is the target.
714
715       -march=architecture[+extension...]
716           Specify which ARM architecture variant is used by the target.
717
718       -mfpu=floating-point-format
719           Select which Floating Point architecture is the target.
720
721       -mfloat-abi=abi
722           Select which floating point ABI is in use.
723
724       -mthumb
725           Enable Thumb only instruction decoding.
726
727       -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
728           Select which procedure calling convention is in use.
729
730       -EB | -EL
731           Select either big-endian (-EB) or little-endian (-EL) output.
732
733       -mthumb-interwork
734           Specify that the code has been generated with interworking between
735           Thumb and ARM code in mind.
736
737       -mccs
738           Turns on CodeComposer Studio assembly syntax compatibility mode.
739
740       -k  Specify that PIC code has been generated.
741
742       The following options are available when as is configured for the
743       Blackfin processor family.
744
745       -mcpu=processor[-sirevision]
746           This option specifies the target processor.  The optional
747           sirevision is not used in assembler.  It's here such that GCC can
748           easily pass down its "-mcpu=" option.  The assembler will issue an
749           error message if an attempt is made to assemble an instruction
750           which will not execute on the target processor.  The following
751           processor names are recognized: "bf504", "bf506", "bf512", "bf514",
752           "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
753           "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
754           implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
755           "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
756           "bf549", "bf549m", "bf561", and "bf592".
757
758       -mfdpic
759           Assemble for the FDPIC ABI.
760
761       -mno-fdpic
762       -mnopic
763           Disable -mfdpic.
764
765       See the info pages for documentation of the CRIS-specific options.
766
767       The following options are available when as is configured for a D10V
768       processor.
769
770       -O  Optimize output by parallelizing instructions.
771
772       The following options are available when as is configured for a D30V
773       processor.
774
775       -O  Optimize output by parallelizing instructions.
776
777       -n  Warn when nops are generated.
778
779       -N  Warn when a nop after a 32-bit multiply instruction is generated.
780
781       The following options are available when as is configured for an
782       Epiphany processor.
783
784       -mepiphany
785           Specifies that the both 32 and 16 bit instructions are allowed.
786           This is the default behavior.
787
788       -mepiphany16
789           Restricts the permitted instructions to just the 16 bit set.
790
791       The following options are available when as is configured for an H8/300
792       processor.  @chapter H8/300 Dependent Features
793
794   Options
795       The Renesas H8/300 version of "as" has one machine-dependent option:
796
797       -h-tick-hex
798           Support H'00 style hex constants in addition to 0x00 style.
799
800       -mach=name
801           Sets the H8300 machine variant.  The following machine names are
802           recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
803           "h8300sxn".
804
805       The following options are available when as is configured for an i386
806       processor.
807
808       --32 | --x32 | --64
809           Select the word size, either 32 bits or 64 bits.  --32 implies
810           Intel i386 architecture, while --x32 and --64 imply AMD x86-64
811           architecture with 32-bit or 64-bit word-size respectively.
812
813           These options are only available with the ELF object file format,
814           and require that the necessary BFD support has been included (on a
815           32-bit platform you have to add --enable-64-bit-bfd to configure
816           enable 64-bit usage and use x86-64 as target platform).
817
818       -n  By default, x86 GAS replaces multiple nop instructions used for
819           alignment within code sections with multi-byte nop instructions
820           such as leal 0(%esi,1),%esi.  This switch disables the optimization
821           if a single byte nop (0x90) is explicitly specified as the fill
822           byte for alignment.
823
824       --divide
825           On SVR4-derived platforms, the character / is treated as a comment
826           character, which means that it cannot be used in expressions.  The
827           --divide option turns / into a normal character.  This does not
828           disable / at the beginning of a line starting a comment, or affect
829           using # for starting a comment.
830
831       -march=CPU[+EXTENSION...]
832           This option specifies the target processor.  The assembler will
833           issue an error message if an attempt is made to assemble an
834           instruction which will not execute on the target processor.  The
835           following processor names are recognized: "i8086", "i186", "i286",
836           "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
837           "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
838           "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
839           "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
840           "bdver3", "bdver4", "znver1", "btver1", "btver2", "generic32" and
841           "generic64".
842
843           In addition to the basic instruction set, the assembler can be told
844           to accept various extension mnemonics.  For example,
845           "-march=i686+sse4+vmx" extends i686 with sse4 and vmx.  The
846           following extensions are currently supported: 8087, 287, 387, 687,
847           "no87", "no287", "no387", "no687", "mmx", "nommx", "sse", "sse2",
848           "sse3", "ssse3", "sse4.1", "sse4.2", "sse4", "nosse", "nosse2",
849           "nosse3", "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx",
850           "avx2", "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap",
851           "mpx", "sha", "rdpid", "ptwrite", "cet", "gfni", "vaes",
852           "vpclmulqdq", "prefetchwt1", "clflushopt", "se1", "clwb",
853           "avx512f", "avx512cd", "avx512er", "avx512pf", "avx512vl",
854           "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi",
855           "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
856           "avx512_vbmi2", "avx512_vnni", "avx512_bitalg", "noavx512f",
857           "noavx512cd", "noavx512er", "noavx512pf", "noavx512vl",
858           "noavx512bw", "noavx512dq", "noavx512ifma", "noavx512vbmi",
859           "noavx512_4fmaps", "noavx512_4vnniw", "noavx512_vpopcntdq",
860           "noavx512_vbmi2", "noavx512_vnni", "noavx512_bitalg", "vmx",
861           "vmfunc", "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes",
862           "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe",
863           "ept", "lzcnt", "hle", "rtm", "invpcid", "clflush", "mwaitx",
864           "clzero", "lwp", "fma4", "xop", "cx16", "syscall", "rdtscp",
865           "3dnow", "3dnowa", "sse4a", "sse5", "svme", "abm" and "padlock".
866           Note that rather than extending a basic instruction set, the
867           extension mnemonics starting with "no" revoke the respective
868           functionality.
869
870           When the ".arch" directive is used with -march, the ".arch"
871           directive will take precedent.
872
873       -mtune=CPU
874           This option specifies a processor to optimize for. When used in
875           conjunction with the -march option, only instructions of the
876           processor specified by the -march option will be generated.
877
878           Valid CPU values are identical to the processor list of -march=CPU.
879
880       -msse2avx
881           This option specifies that the assembler should encode SSE
882           instructions with VEX prefix.
883
884       -msse-check=none
885       -msse-check=warning
886       -msse-check=error
887           These options control if the assembler should check SSE
888           instructions.  -msse-check=none will make the assembler not to
889           check SSE instructions,  which is the default.  -msse-check=warning
890           will make the assembler issue a warning for any SSE instruction.
891           -msse-check=error will make the assembler issue an error for any
892           SSE instruction.
893
894       -mavxscalar=128
895       -mavxscalar=256
896           These options control how the assembler should encode scalar AVX
897           instructions.  -mavxscalar=128 will encode scalar AVX instructions
898           with 128bit vector length, which is the default.  -mavxscalar=256
899           will encode scalar AVX instructions with 256bit vector length.
900
901       -mevexlig=128
902       -mevexlig=256
903       -mevexlig=512
904           These options control how the assembler should encode length-
905           ignored (LIG) EVEX instructions.  -mevexlig=128 will encode LIG
906           EVEX instructions with 128bit vector length, which is the default.
907           -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
908           with 256bit and 512bit vector length, respectively.
909
910       -mevexwig=0
911       -mevexwig=1
912           These options control how the assembler should encode w-ignored
913           (WIG) EVEX instructions.  -mevexwig=0 will encode WIG EVEX
914           instructions with evex.w = 0, which is the default.  -mevexwig=1
915           will encode WIG EVEX instructions with evex.w = 1.
916
917       -mmnemonic=att
918       -mmnemonic=intel
919           This option specifies instruction mnemonic for matching
920           instructions.  The ".att_mnemonic" and ".intel_mnemonic" directives
921           will take precedent.
922
923       -msyntax=att
924       -msyntax=intel
925           This option specifies instruction syntax when processing
926           instructions.  The ".att_syntax" and ".intel_syntax" directives
927           will take precedent.
928
929       -mnaked-reg
930           This option specifies that registers don't require a % prefix.  The
931           ".att_syntax" and ".intel_syntax" directives will take precedent.
932
933       -madd-bnd-prefix
934           This option forces the assembler to add BND prefix to all branches,
935           even if such prefix was not explicitly specified in the source
936           code.
937
938       -mno-shared
939           On ELF target, the assembler normally optimizes out non-PLT
940           relocations against defined non-weak global branch targets with
941           default visibility.  The -mshared option tells the assembler to
942           generate code which may go into a shared library where all non-weak
943           global branch targets with default visibility can be preempted.
944           The resulting code is slightly bigger.  This option only affects
945           the handling of branch instructions.
946
947       -mbig-obj
948           On x86-64 PE/COFF target this option forces the use of big object
949           file format, which allows more than 32768 sections.
950
951       -momit-lock-prefix=no
952       -momit-lock-prefix=yes
953           These options control how the assembler should encode lock prefix.
954           This option is intended as a workaround for processors, that fail
955           on lock prefix. This option can only be safely used with single-
956           core, single-thread computers -momit-lock-prefix=yes will omit all
957           lock prefixes.  -momit-lock-prefix=no will encode lock prefix as
958           usual, which is the default.
959
960       -mfence-as-lock-add=no
961       -mfence-as-lock-add=yes
962           These options control how the assembler should encode lfence,
963           mfence and sfence.  -mfence-as-lock-add=yes will encode lfence,
964           mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
965           addl $0x0, (%esp) in 32-bit mode.  -mfence-as-lock-add=no will
966           encode lfence, mfence and sfence as usual, which is the default.
967
968       -mrelax-relocations=no
969       -mrelax-relocations=yes
970           These options control whether the assembler should generate relax
971           relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
972           and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
973           -mrelax-relocations=yes will generate relax relocations.
974           -mrelax-relocations=no will not generate relax relocations.  The
975           default can be controlled by a configure option
976           --enable-x86-relax-relocations.
977
978       -mevexrcig=rne
979       -mevexrcig=rd
980       -mevexrcig=ru
981       -mevexrcig=rz
982           These options control how the assembler should encode SAE-only EVEX
983           instructions.  -mevexrcig=rne will encode RC bits of EVEX
984           instruction with 00, which is the default.  -mevexrcig=rd,
985           -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
986           instructions with 01, 10 and 11 RC bits, respectively.
987
988       -mamd64
989       -mintel64
990           This option specifies that the assembler should accept only AMD64
991           or Intel64 ISA in 64-bit mode.  The default is to accept both.
992
993       The following options are available when as is configured for the Intel
994       80960 processor.
995
996       -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
997           Specify which variant of the 960 architecture is the target.
998
999       -b  Add code to collect statistics about branches taken.
1000
1001       -no-relax
1002           Do not alter compare-and-branch instructions for long
1003           displacements; error if necessary.
1004
1005       The following options are available when as is configured for the
1006       Ubicom IP2K series.
1007
1008       -mip2022ext
1009           Specifies that the extended IP2022 instructions are allowed.
1010
1011       -mip2022
1012           Restores the default behaviour, which restricts the permitted
1013           instructions to just the basic IP2022 ones.
1014
1015       The following options are available when as is configured for the
1016       Renesas M32C and M16C processors.
1017
1018       -m32c
1019           Assemble M32C instructions.
1020
1021       -m16c
1022           Assemble M16C instructions (the default).
1023
1024       -relax
1025           Enable support for link-time relaxations.
1026
1027       -h-tick-hex
1028           Support H'00 style hex constants in addition to 0x00 style.
1029
1030       The following options are available when as is configured for the
1031       Renesas M32R (formerly Mitsubishi M32R) series.
1032
1033       --m32rx
1034           Specify which processor in the M32R family is the target.  The
1035           default is normally the M32R, but this option changes it to the
1036           M32RX.
1037
1038       --warn-explicit-parallel-conflicts or --Wp
1039           Produce warning messages when questionable parallel constructs are
1040           encountered.
1041
1042       --no-warn-explicit-parallel-conflicts or --Wnp
1043           Do not produce warning messages when questionable parallel
1044           constructs are encountered.
1045
1046       The following options are available when as is configured for the
1047       Motorola 68000 series.
1048
1049       -l  Shorten references to undefined symbols, to one word instead of
1050           two.
1051
1052       -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1053       | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1054       | -m68333 | -m68340 | -mcpu32 | -m5200
1055           Specify what processor in the 68000 family is the target.  The
1056           default is normally the 68020, but this can be changed at
1057           configuration time.
1058
1059       -m68881 | -m68882 | -mno-68881 | -mno-68882
1060           The target machine does (or does not) have a floating-point
1061           coprocessor.  The default is to assume a coprocessor for 68020,
1062           68030, and cpu32.  Although the basic 68000 is not compatible with
1063           the 68881, a combination of the two can be specified, since it's
1064           possible to do emulation of the coprocessor instructions with the
1065           main processor.
1066
1067       -m68851 | -mno-68851
1068           The target machine does (or does not) have a memory-management unit
1069           coprocessor.  The default is to assume an MMU for 68020 and up.
1070
1071       The following options are available when as is configured for an Altera
1072       Nios II processor.
1073
1074       -relax-section
1075           Replace identified out-of-range branches with PC-relative "jmp"
1076           sequences when possible.  The generated code sequences are suitable
1077           for use in position-independent code, but there is a practical
1078           limit on the extended branch range because of the length of the
1079           sequences.  This option is the default.
1080
1081       -relax-all
1082           Replace branch instructions not determinable to be in range and all
1083           call instructions with "jmp" and "callr" sequences (respectively).
1084           This option generates absolute relocations against the target
1085           symbols and is not appropriate for position-independent code.
1086
1087       -no-relax
1088           Do not replace any branches or calls.
1089
1090       -EB Generate big-endian output.
1091
1092       -EL Generate little-endian output.  This is the default.
1093
1094       -march=architecture
1095           This option specifies the target architecture.  The assembler
1096           issues an error message if an attempt is made to assemble an
1097           instruction which will not execute on the target architecture.  The
1098           following architecture names are recognized: "r1", "r2".  The
1099           default is "r1".
1100
1101       The following options are available when as is configured for a PRU
1102       processor.
1103
1104       -mlink-relax
1105           Assume that LD would optimize LDI32 instructions by checking the
1106           upper 16 bits of the expression. If they are all zeros, then LD
1107           would shorten the LDI32 instruction to a single LDI. In such case
1108           "as" will output DIFF relocations for diff expressions.
1109
1110       -mno-link-relax
1111           Assume that LD would not optimize LDI32 instructions. As a
1112           consequence, DIFF relocations will not be emitted.
1113
1114       -mno-warn-regname-label
1115           Do not warn if a label name matches a register name. Usually
1116           assembler programmers will want this warning to be emitted. C
1117           compilers may want to turn this off.
1118
1119       The following options are available when as is configured for a MIPS
1120       processor.
1121
1122       -G num
1123           This option sets the largest size of an object that can be
1124           referenced implicitly with the "gp" register.  It is only accepted
1125           for targets that use ECOFF format, such as a DECstation running
1126           Ultrix.  The default value is 8.
1127
1128       -EB Generate "big endian" format output.
1129
1130       -EL Generate "little endian" format output.
1131
1132       -mips1
1133       -mips2
1134       -mips3
1135       -mips4
1136       -mips5
1137       -mips32
1138       -mips32r2
1139       -mips32r3
1140       -mips32r5
1141       -mips32r6
1142       -mips64
1143       -mips64r2
1144       -mips64r3
1145       -mips64r5
1146       -mips64r6
1147           Generate code for a particular MIPS Instruction Set Architecture
1148           level.  -mips1 is an alias for -march=r3000, -mips2 is an alias for
1149           -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1150           alias for -march=r8000.  -mips5, -mips32, -mips32r2, -mips32r3,
1151           -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1152           -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1153           MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1154           MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1155           Release 6 ISA processors, respectively.
1156
1157       -march=cpu
1158           Generate code for a particular MIPS CPU.
1159
1160       -mtune=cpu
1161           Schedule and tune for a particular MIPS CPU.
1162
1163       -mfix7000
1164       -mno-fix7000
1165           Cause nops to be inserted if the read of the destination register
1166           of an mfhi or mflo instruction occurs in the following two
1167           instructions.
1168
1169       -mfix-rm7000
1170       -mno-fix-rm7000
1171           Cause nops to be inserted if a dmult or dmultu instruction is
1172           followed by a load instruction.
1173
1174       -mdebug
1175       -no-mdebug
1176           Cause stabs-style debugging output to go into an ECOFF-style
1177           .mdebug section instead of the standard ELF .stabs sections.
1178
1179       -mpdr
1180       -mno-pdr
1181           Control generation of ".pdr" sections.
1182
1183       -mgp32
1184       -mfp32
1185           The register sizes are normally inferred from the ISA and ABI, but
1186           these flags force a certain group of registers to be treated as 32
1187           bits wide at all times.  -mgp32 controls the size of general-
1188           purpose registers and -mfp32 controls the size of floating-point
1189           registers.
1190
1191       -mgp64
1192       -mfp64
1193           The register sizes are normally inferred from the ISA and ABI, but
1194           these flags force a certain group of registers to be treated as 64
1195           bits wide at all times.  -mgp64 controls the size of general-
1196           purpose registers and -mfp64 controls the size of floating-point
1197           registers.
1198
1199       -mfpxx
1200           The register sizes are normally inferred from the ISA and ABI, but
1201           using this flag in combination with -mabi=32 enables an ABI variant
1202           which will operate correctly with floating-point registers which
1203           are 32 or 64 bits wide.
1204
1205       -modd-spreg
1206       -mno-odd-spreg
1207           Enable use of floating-point operations on odd-numbered single-
1208           precision registers when supported by the ISA.  -mfpxx implies
1209           -mno-odd-spreg, otherwise the default is -modd-spreg.
1210
1211       -mips16
1212       -no-mips16
1213           Generate code for the MIPS 16 processor.  This is equivalent to
1214           putting ".module mips16" at the start of the assembly file.
1215           -no-mips16 turns off this option.
1216
1217       -mmips16e2
1218       -mno-mips16e2
1219           Enable the use of MIPS16e2 instructions in MIPS16 mode.  This is
1220           equivalent to putting ".module mips16e2" at the start of the
1221           assembly file.  -mno-mips16e2 turns off this option.
1222
1223       -mmicromips
1224       -mno-micromips
1225           Generate code for the microMIPS processor.  This is equivalent to
1226           putting ".module micromips" at the start of the assembly file.
1227           -mno-micromips turns off this option.  This is equivalent to
1228           putting ".module nomicromips" at the start of the assembly file.
1229
1230       -msmartmips
1231       -mno-smartmips
1232           Enables the SmartMIPS extension to the MIPS32 instruction set.
1233           This is equivalent to putting ".module smartmips" at the start of
1234           the assembly file.  -mno-smartmips turns off this option.
1235
1236       -mips3d
1237       -no-mips3d
1238           Generate code for the MIPS-3D Application Specific Extension.  This
1239           tells the assembler to accept MIPS-3D instructions.  -no-mips3d
1240           turns off this option.
1241
1242       -mdmx
1243       -no-mdmx
1244           Generate code for the MDMX Application Specific Extension.  This
1245           tells the assembler to accept MDMX instructions.  -no-mdmx turns
1246           off this option.
1247
1248       -mdsp
1249       -mno-dsp
1250           Generate code for the DSP Release 1 Application Specific Extension.
1251           This tells the assembler to accept DSP Release 1 instructions.
1252           -mno-dsp turns off this option.
1253
1254       -mdspr2
1255       -mno-dspr2
1256           Generate code for the DSP Release 2 Application Specific Extension.
1257           This option implies -mdsp.  This tells the assembler to accept DSP
1258           Release 2 instructions.  -mno-dspr2 turns off this option.
1259
1260       -mdspr3
1261       -mno-dspr3
1262           Generate code for the DSP Release 3 Application Specific Extension.
1263           This option implies -mdsp and -mdspr2.  This tells the assembler to
1264           accept DSP Release 3 instructions.  -mno-dspr3 turns off this
1265           option.
1266
1267       -mmsa
1268       -mno-msa
1269           Generate code for the MIPS SIMD Architecture Extension.  This tells
1270           the assembler to accept MSA instructions.  -mno-msa turns off this
1271           option.
1272
1273       -mxpa
1274       -mno-xpa
1275           Generate code for the MIPS eXtended Physical Address (XPA)
1276           Extension.  This tells the assembler to accept XPA instructions.
1277           -mno-xpa turns off this option.
1278
1279       -mmt
1280       -mno-mt
1281           Generate code for the MT Application Specific Extension.  This
1282           tells the assembler to accept MT instructions.  -mno-mt turns off
1283           this option.
1284
1285       -mmcu
1286       -mno-mcu
1287           Generate code for the MCU Application Specific Extension.  This
1288           tells the assembler to accept MCU instructions.  -mno-mcu turns off
1289           this option.
1290
1291       -minsn32
1292       -mno-insn32
1293           Only use 32-bit instruction encodings when generating code for the
1294           microMIPS processor.  This option inhibits the use of any 16-bit
1295           instructions.  This is equivalent to putting ".set insn32" at the
1296           start of the assembly file.  -mno-insn32 turns off this option.
1297           This is equivalent to putting ".set noinsn32" at the start of the
1298           assembly file.  By default -mno-insn32 is selected, allowing all
1299           instructions to be used.
1300
1301       --construct-floats
1302       --no-construct-floats
1303           The --no-construct-floats option disables the construction of
1304           double width floating point constants by loading the two halves of
1305           the value into the two single width floating point registers that
1306           make up the double width register.  By default --construct-floats
1307           is selected, allowing construction of these floating point
1308           constants.
1309
1310       --relax-branch
1311       --no-relax-branch
1312           The --relax-branch option enables the relaxation of out-of-range
1313           branches.  By default --no-relax-branch is selected, causing any
1314           out-of-range branches to produce an error.
1315
1316       -mignore-branch-isa
1317       -mno-ignore-branch-isa
1318           Ignore branch checks for invalid transitions between ISA modes.
1319           The semantics of branches does not provide for an ISA mode switch,
1320           so in most cases the ISA mode a branch has been encoded for has to
1321           be the same as the ISA mode of the branch's target label.
1322           Therefore GAS has checks implemented that verify in branch assembly
1323           that the two ISA modes match.  -mignore-branch-isa disables these
1324           checks.  By default -mno-ignore-branch-isa is selected, causing any
1325           invalid branch requiring a transition between ISA modes to produce
1326           an error.
1327
1328       -mnan=encoding
1329           Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1330           (-mnan=legacy) NaN encoding format.  The latter is the default.
1331
1332       --emulation=name
1333           This option was formerly used to switch between ELF and ECOFF
1334           output on targets like IRIX 5 that supported both.  MIPS ECOFF
1335           support was removed in GAS 2.24, so the option now serves little
1336           purpose.  It is retained for backwards compatibility.
1337
1338           The available configuration names are: mipself, mipslelf and
1339           mipsbelf.  Choosing mipself now has no effect, since the output is
1340           always ELF.  mipslelf and mipsbelf select little- and big-endian
1341           output respectively, but -EL and -EB are now the preferred options
1342           instead.
1343
1344       -nocpp
1345           as ignores this option.  It is accepted for compatibility with the
1346           native tools.
1347
1348       --trap
1349       --no-trap
1350       --break
1351       --no-break
1352           Control how to deal with multiplication overflow and division by
1353           zero.  --trap or --no-break (which are synonyms) take a trap
1354           exception (and only work for Instruction Set Architecture level 2
1355           and higher); --break or --no-trap (also synonyms, and the default)
1356           take a break exception.
1357
1358       -n  When this option is used, as will issue a warning every time it
1359           generates a nop instruction from a macro.
1360
1361       The following options are available when as is configured for a Meta
1362       processor.
1363
1364       "-mcpu=metac11"
1365           Generate code for Meta 1.1.
1366
1367       "-mcpu=metac12"
1368           Generate code for Meta 1.2.
1369
1370       "-mcpu=metac21"
1371           Generate code for Meta 2.1.
1372
1373       "-mfpu=metac21"
1374           Allow code to use FPU hardware of Meta 2.1.
1375
1376       See the info pages for documentation of the MMIX-specific options.
1377
1378       The following options are available when as is configured for a NDS32
1379       processor.
1380
1381       "-O1"
1382           Optimize for performance.
1383
1384       "-Os"
1385           Optimize for space.
1386
1387       "-EL"
1388           Produce little endian data output.
1389
1390       "-EB"
1391           Produce little endian data output.
1392
1393       "-mpic"
1394           Generate PIC.
1395
1396       "-mno-fp-as-gp-relax"
1397           Suppress fp-as-gp relaxation for this file.
1398
1399       "-mb2bb-relax"
1400           Back-to-back branch optimization.
1401
1402       "-mno-all-relax"
1403           Suppress all relaxation for this file.
1404
1405       "-march=<arch name>"
1406           Assemble for architecture <arch name> which could be v3, v3j, v3m,
1407           v3f, v3s, v2, v2j, v2f, v2s.
1408
1409       "-mbaseline=<baseline>"
1410           Assemble for baseline <baseline> which could be v2, v3, v3m.
1411
1412       "-mfpu-freg=FREG"
1413           Specify a FPU configuration.
1414
1415           "0      8 SP /  4 DP registers"
1416           "1     16 SP /  8 DP registers"
1417           "2     32 SP / 16 DP registers"
1418           "3     32 SP / 32 DP registers"
1419       "-mabi=abi"
1420           Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1421
1422       "-m[no-]mac"
1423           Enable/Disable Multiply instructions support.
1424
1425       "-m[no-]div"
1426           Enable/Disable Divide instructions support.
1427
1428       "-m[no-]16bit-ext"
1429           Enable/Disable 16-bit extension
1430
1431       "-m[no-]dx-regs"
1432           Enable/Disable d0/d1 registers
1433
1434       "-m[no-]perf-ext"
1435           Enable/Disable Performance extension
1436
1437       "-m[no-]perf2-ext"
1438           Enable/Disable Performance extension 2
1439
1440       "-m[no-]string-ext"
1441           Enable/Disable String extension
1442
1443       "-m[no-]reduced-regs"
1444           Enable/Disable Reduced Register configuration (GPR16) option
1445
1446       "-m[no-]audio-isa-ext"
1447           Enable/Disable AUDIO ISA extension
1448
1449       "-m[no-]fpu-sp-ext"
1450           Enable/Disable FPU SP extension
1451
1452       "-m[no-]fpu-dp-ext"
1453           Enable/Disable FPU DP extension
1454
1455       "-m[no-]fpu-fma"
1456           Enable/Disable FPU fused-multiply-add instructions
1457
1458       "-mall-ext"
1459           Turn on all extensions and instructions support
1460
1461       The following options are available when as is configured for a PowerPC
1462       processor.
1463
1464       -a32
1465           Generate ELF32 or XCOFF32.
1466
1467       -a64
1468           Generate ELF64 or XCOFF64.
1469
1470       -K PIC
1471           Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1472
1473       -mpwrx | -mpwr2
1474           Generate code for POWER/2 (RIOS2).
1475
1476       -mpwr
1477           Generate code for POWER (RIOS1)
1478
1479       -m601
1480           Generate code for PowerPC 601.
1481
1482       -mppc, -mppc32, -m603, -m604
1483           Generate code for PowerPC 603/604.
1484
1485       -m403, -m405
1486           Generate code for PowerPC 403/405.
1487
1488       -m440
1489           Generate code for PowerPC 440.  BookE and some 405 instructions.
1490
1491       -m464
1492           Generate code for PowerPC 464.
1493
1494       -m476
1495           Generate code for PowerPC 476.
1496
1497       -m7400, -m7410, -m7450, -m7455
1498           Generate code for PowerPC 7400/7410/7450/7455.
1499
1500       -m750cl
1501           Generate code for PowerPC 750CL.
1502
1503       -m821, -m850, -m860
1504           Generate code for PowerPC 821/850/860.
1505
1506       -mppc64, -m620
1507           Generate code for PowerPC 620/625/630.
1508
1509       -me500, -me500x2
1510           Generate code for Motorola e500 core complex.
1511
1512       -me500mc
1513           Generate code for Freescale e500mc core complex.
1514
1515       -me500mc64
1516           Generate code for Freescale e500mc64 core complex.
1517
1518       -me5500
1519           Generate code for Freescale e5500 core complex.
1520
1521       -me6500
1522           Generate code for Freescale e6500 core complex.
1523
1524       -mspe
1525           Generate code for Motorola SPE instructions.
1526
1527       -mspe2
1528           Generate code for Freescale SPE2 instructions.
1529
1530       -mtitan
1531           Generate code for AppliedMicro Titan core complex.
1532
1533       -mppc64bridge
1534           Generate code for PowerPC 64, including bridge insns.
1535
1536       -mbooke
1537           Generate code for 32-bit BookE.
1538
1539       -ma2
1540           Generate code for A2 architecture.
1541
1542       -me300
1543           Generate code for PowerPC e300 family.
1544
1545       -maltivec
1546           Generate code for processors with AltiVec instructions.
1547
1548       -mvle
1549           Generate code for Freescale PowerPC VLE instructions.
1550
1551       -mvsx
1552           Generate code for processors with Vector-Scalar (VSX) instructions.
1553
1554       -mhtm
1555           Generate code for processors with Hardware Transactional Memory
1556           instructions.
1557
1558       -mpower4, -mpwr4
1559           Generate code for Power4 architecture.
1560
1561       -mpower5, -mpwr5, -mpwr5x
1562           Generate code for Power5 architecture.
1563
1564       -mpower6, -mpwr6
1565           Generate code for Power6 architecture.
1566
1567       -mpower7, -mpwr7
1568           Generate code for Power7 architecture.
1569
1570       -mpower8, -mpwr8
1571           Generate code for Power8 architecture.
1572
1573       -mpower9, -mpwr9
1574           Generate code for Power9 architecture.
1575
1576       -mcell
1577       -mcell
1578           Generate code for Cell Broadband Engine architecture.
1579
1580       -mcom
1581           Generate code Power/PowerPC common instructions.
1582
1583       -many
1584           Generate code for any architecture (PWR/PWRX/PPC).
1585
1586       -mregnames
1587           Allow symbolic names for registers.
1588
1589       -mno-regnames
1590           Do not allow symbolic names for registers.
1591
1592       -mrelocatable
1593           Support for GCC's -mrelocatable option.
1594
1595       -mrelocatable-lib
1596           Support for GCC's -mrelocatable-lib option.
1597
1598       -memb
1599           Set PPC_EMB bit in ELF flags.
1600
1601       -mlittle, -mlittle-endian, -le
1602           Generate code for a little endian machine.
1603
1604       -mbig, -mbig-endian, -be
1605           Generate code for a big endian machine.
1606
1607       -msolaris
1608           Generate code for Solaris.
1609
1610       -mno-solaris
1611           Do not generate code for Solaris.
1612
1613       -nops=count
1614           If an alignment directive inserts more than count nops, put a
1615           branch at the beginning to skip execution of the nops.
1616
1617       The following options are available when as is configured for a RISC-V
1618       processor.
1619
1620       -fpic
1621       -fPIC
1622           Generate position-independent code
1623
1624       -fno-pic
1625           Don't generate position-independent code (default)
1626
1627       -march=ISA
1628           Select the base isa, as specified by ISA.  For example
1629           -march=rv32ima.
1630
1631       -mabi=ABI
1632           Selects the ABI, which is either "ilp32" or "lp64", optionally
1633           followed by "f", "d", or "q" to indicate single-precision, double-
1634           precision, or quad-precision floating-point calling convention, or
1635           none to indicate the soft-float calling convention.
1636
1637       See the info pages for documentation of the RX-specific options.
1638
1639       The following options are available when as is configured for the s390
1640       processor family.
1641
1642       -m31
1643       -m64
1644           Select the word size, either 31/32 bits or 64 bits.
1645
1646       -mesa
1647       -mzarch
1648           Select the architecture mode, either the Enterprise System
1649           Architecture (esa) or the z/Architecture mode (zarch).
1650
1651       -march=processor
1652           Specify which s390 processor variant is the target, g5 (or arch3),
1653           g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
1654           (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), or
1655           z14 (or arch12).
1656
1657       -mregnames
1658       -mno-regnames
1659           Allow or disallow symbolic names for registers.
1660
1661       -mwarn-areg-zero
1662           Warn whenever the operand for a base or index register has been
1663           specified but evaluates to zero.
1664
1665       The following options are available when as is configured for a
1666       TMS320C6000 processor.
1667
1668       -march=arch
1669           Enable (only) instructions from architecture arch.  By default, all
1670           instructions are permitted.
1671
1672           The following values of arch are accepted: "c62x", "c64x", "c64x+",
1673           "c67x", "c67x+", "c674x".
1674
1675       -mdsbt
1676       -mno-dsbt
1677           The -mdsbt option causes the assembler to generate the
1678           "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1679           code is using DSBT addressing.  The -mno-dsbt option, the default,
1680           causes the tag to have a value of 0, indicating that the code does
1681           not use DSBT addressing.  The linker will emit a warning if objects
1682           of different type (DSBT and non-DSBT) are linked together.
1683
1684       -mpid=no
1685       -mpid=near
1686       -mpid=far
1687           The -mpid= option causes the assembler to generate the
1688           "Tag_ABI_PID" attribute with a value indicating the form of data
1689           addressing used by the code.  -mpid=no, the default, indicates
1690           position-dependent data addressing, -mpid=near indicates position-
1691           independent addressing with GOT accesses using near DP addressing,
1692           and -mpid=far indicates position-independent addressing with GOT
1693           accesses using far DP addressing.  The linker will emit a warning
1694           if objects built with different settings of this option are linked
1695           together.
1696
1697       -mpic
1698       -mno-pic
1699           The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1700           attribute with a value of 1, indicating that the code is using
1701           position-independent code addressing,  The "-mno-pic" option, the
1702           default, causes the tag to have a value of 0, indicating position-
1703           dependent code addressing.  The linker will emit a warning if
1704           objects of different type (position-dependent and position-
1705           independent) are linked together.
1706
1707       -mbig-endian
1708       -mlittle-endian
1709           Generate code for the specified endianness.  The default is little-
1710           endian.
1711
1712       The following options are available when as is configured for a TILE-Gx
1713       processor.
1714
1715       -m32 | -m64
1716           Select the word size, either 32 bits or 64 bits.
1717
1718       -EB | -EL
1719           Select the endianness, either big-endian (-EB) or little-endian
1720           (-EL).
1721
1722       The following option is available when as is configured for a Visium
1723       processor.
1724
1725       -mtune=arch
1726           This option specifies the target architecture.  If an attempt is
1727           made to assemble an instruction that will not execute on the target
1728           architecture, the assembler will issue an error message.
1729
1730           The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
1731
1732       The following options are available when as is configured for an Xtensa
1733       processor.
1734
1735       --text-section-literals | --no-text-section-literals
1736           Control the treatment of literal pools.  The default is
1737           --no-text-section-literals, which places literals in separate
1738           sections in the output file.  This allows the literal pool to be
1739           placed in a data RAM/ROM.  With --text-section-literals, the
1740           literals are interspersed in the text section in order to keep them
1741           as close as possible to their references.  This may be necessary
1742           for large assembly files, where the literals would otherwise be out
1743           of range of the "L32R" instructions in the text section.  Literals
1744           are grouped into pools following ".literal_position" directives or
1745           preceding "ENTRY" instructions.  These options only affect literals
1746           referenced via PC-relative "L32R" instructions; literals for
1747           absolute mode "L32R" instructions are handled separately.
1748
1749       --auto-litpools | --no-auto-litpools
1750           Control the treatment of literal pools.  The default is
1751           --no-auto-litpools, which in the absence of --text-section-literals
1752           places literals in separate sections in the output file.  This
1753           allows the literal pool to be placed in a data RAM/ROM.  With
1754           --auto-litpools, the literals are interspersed in the text section
1755           in order to keep them as close as possible to their references,
1756           explicit ".literal_position" directives are not required.  This may
1757           be necessary for very large functions, where single literal pool at
1758           the beginning of the function may not be reachable by "L32R"
1759           instructions at the end.  These options only affect literals
1760           referenced via PC-relative "L32R" instructions; literals for
1761           absolute mode "L32R" instructions are handled separately.  When
1762           used together with --text-section-literals, --auto-litpools takes
1763           precedence.
1764
1765       --absolute-literals | --no-absolute-literals
1766           Indicate to the assembler whether "L32R" instructions use absolute
1767           or PC-relative addressing.  If the processor includes the absolute
1768           addressing option, the default is to use absolute "L32R"
1769           relocations.  Otherwise, only the PC-relative "L32R" relocations
1770           can be used.
1771
1772       --target-align | --no-target-align
1773           Enable or disable automatic alignment to reduce branch penalties at
1774           some expense in code size.    This optimization is enabled by
1775           default.  Note that the assembler will always align instructions
1776           like "LOOP" that have fixed alignment requirements.
1777
1778       --longcalls | --no-longcalls
1779           Enable or disable transformation of call instructions to allow
1780           calls across a greater range of addresses.    This option should be
1781           used when call targets can potentially be out of range.  It may
1782           degrade both code size and performance, but the linker can
1783           generally optimize away the unnecessary overhead when a call ends
1784           up within range.  The default is --no-longcalls.
1785
1786       --transform | --no-transform
1787           Enable or disable all assembler transformations of Xtensa
1788           instructions, including both relaxation and optimization.  The
1789           default is --transform; --no-transform should only be used in the
1790           rare cases when the instructions must be exactly as specified in
1791           the assembly source.  Using --no-transform causes out of range
1792           instruction operands to be errors.
1793
1794       --rename-section oldname=newname
1795           Rename the oldname section to newname.  This option can be used
1796           multiple times to rename multiple sections.
1797
1798       --trampolines | --no-trampolines
1799           Enable or disable transformation of jump instructions to allow
1800           jumps across a greater range of addresses.    This option should be
1801           used when jump targets can potentially be out of range.  In the
1802           absence of such jumps this option does not affect code size or
1803           performance.  The default is --trampolines.
1804
1805       The following options are available when as is configured for a Z80
1806       family processor.
1807
1808       -z80
1809           Assemble for Z80 processor.
1810
1811       -r800
1812           Assemble for R800 processor.
1813
1814       -ignore-undocumented-instructions
1815       -Wnud
1816           Assemble undocumented Z80 instructions that also work on R800
1817           without warning.
1818
1819       -ignore-unportable-instructions
1820       -Wnup
1821           Assemble all undocumented Z80 instructions without warning.
1822
1823       -warn-undocumented-instructions
1824       -Wud
1825           Issue a warning for undocumented Z80 instructions that also work on
1826           R800.
1827
1828       -warn-unportable-instructions
1829       -Wup
1830           Issue a warning for undocumented Z80 instructions that do not work
1831           on R800.
1832
1833       -forbid-undocumented-instructions
1834       -Fud
1835           Treat all undocumented instructions as errors.
1836
1837       -forbid-unportable-instructions
1838       -Fup
1839           Treat undocumented Z80 instructions that do not work on R800 as
1840           errors.
1841

SEE ALSO

1843       gcc(1), ld(1), and the Info entries for binutils and ld.
1844
1846       Copyright (c) 1991-2018 Free Software Foundation, Inc.
1847
1848       Permission is granted to copy, distribute and/or modify this document
1849       under the terms of the GNU Free Documentation License, Version 1.3 or
1850       any later version published by the Free Software Foundation; with no
1851       Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
1852       Texts.  A copy of the license is included in the section entitled "GNU
1853       Free Documentation License".
1854
1855
1856
1857binutils-2.30                     2018-07-13                             AS(1)
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