1AS(1) GNU Development Tools AS(1)
2
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14 [--help] [-I dir] [-J]
15 [-K] [-L] [--listing-lhs-width=NUM]
16 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
17 [--listing-cont-lines=NUM] [--keep-locals]
18 [--no-pad-sections]
19 [-o objfile] [-R]
20 [--hash-size=NUM] [--reduce-memory-overheads]
21 [--statistics]
22 [-v] [-version] [--version]
23 [-W] [--warn] [--fatal-warnings] [-w] [-x]
24 [-Z] [@FILE]
25 [--sectname-subst] [--size-check=[error|warning]]
26 [--elf-stt-common=[no|yes]]
27 [--target-help] [target-options]
28 [--|files ...]
29
31 Target AArch64 options:
32 [-EB|-EL]
33 [-mabi=ABI]
34 Target Alpha options:
36 [-mcpu]
37 [-mdebug | -no-mdebug]
38 [-replace | -noreplace]
39 [-relax] [-g] [-Gsize]
40 [-F] [-32addr]
41 Target ARC options:
43 [-mcpu=cpu]
44 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
45 [-mcode-density]
46 [-mrelax]
47 [-EB|-EL]
48 Target ARM options:
50 [-mcpu=processor[+extension...]]
51 [-march=architecture[+extension...]]
52 [-mfpu=floating-point-format]
53 [-mfloat-abi=abi]
54 [-meabi=ver]
55 [-mthumb]
56 [-EB|-EL]
57 [-mapcs-32|-mapcs-26|-mapcs-float|
58 -mapcs-reentrant]
59 [-mthumb-interwork] [-k]
60 Target Blackfin options:
62 [-mcpu=processor[-sirevision]]
63 [-mfdpic]
64 [-mno-fdpic]
65 [-mnopic]
66 Target CRIS options:
68 [--underscore | --no-underscore]
69 [--pic] [-N]
70 [--emulation=criself | --emulation=crisaout]
71 [--march=v0_v10 | --march=v10 | --march=v32 |
72 --march=common_v10_v32]
73 Target D10V options:
75 [-O]
76 Target D30V options:
78 [-O|-n|-N]
79 Target EPIPHANY options:
81 [-mepiphany|-mepiphany16]
82 Target H8/300 options:
84 [-h-tick-hex]
85 Target i386 options:
87 [--32|--x32|--64] [-n]
88 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
89 Target i960 options:
91 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
92 -AKC|-AMC]
93 [-b] [-no-relax]
94 Target IA-64 options:
96 [-mconstant-gp|-mauto-pic]
97 [-milp32|-milp64|-mlp64|-mp64]
98 [-mle|mbe]
99 [-mtune=itanium1|-mtune=itanium2]
100 [-munwind-check=warning|-munwind-check=error]
101 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
102 [-x|-xexplicit] [-xauto] [-xdebug]
103 Target IP2K options:
105 [-mip2022|-mip2022ext]
106 Target M32C options:
108 [-m32c|-m16c] [-relax] [-h-tick-hex]
109 Target M32R options:
111 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
112 --W[n]p]
113 Target M680X0 options:
115 [-l] [-m68000|-m68010|-m68020|...]
116 Target M68HC11 options:
118 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
119 [-mshort|-mlong]
120 [-mshort-double|-mlong-double]
121 [--force-long-branches] [--short-branches]
122 [--strict-direct-mode] [--print-insn-syntax]
123 [--print-opcodes] [--generate-example]
124 Target MCORE options:
126 [-jsri2bsr] [-sifilter] [-relax]
127 [-mcpu=[210|340]]
128 Target Meta options:
130 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
131 Target MIPS options:
133 [-nocpp] [-EL] [-EB] [-O[optimization level]]
134 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
135 [-non_shared] [-xgot [-mvxworks-pic]
136 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
137 [-mfp64] [-mgp64] [-mfpxx]
138 [-modd-spreg] [-mno-odd-spreg]
139 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
140 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
141 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
142 [-mips64r3] [-mips64r5] [-mips64r6]
143 [-construct-floats] [-no-construct-floats]
144 [-mignore-branch-isa] [-mno-ignore-branch-isa]
145 [-mnan=encoding]
146 [-trap] [-no-break] [-break] [-no-trap]
147 [-mips16] [-no-mips16]
148 [-mmips16e2] [-mno-mips16e2]
149 [-mmicromips] [-mno-micromips]
150 [-msmartmips] [-mno-smartmips]
151 [-mips3d] [-no-mips3d]
152 [-mdmx] [-no-mdmx]
153 [-mdsp] [-mno-dsp]
154 [-mdspr2] [-mno-dspr2]
155 [-mdspr3] [-mno-dspr3]
156 [-mmsa] [-mno-msa]
157 [-mxpa] [-mno-xpa]
158 [-mmt] [-mno-mt]
159 [-mmcu] [-mno-mcu]
160 [-minsn32] [-mno-insn32]
161 [-mfix7000] [-mno-fix7000]
162 [-mfix-rm7000] [-mno-fix-rm7000]
163 [-mfix-vr4120] [-mno-fix-vr4120]
164 [-mfix-vr4130] [-mno-fix-vr4130]
165 [-mdebug] [-no-mdebug]
166 [-mpdr] [-mno-pdr]
167 Target MMIX options:
169 [--fixed-special-register-names] [--globalize-symbols]
170 [--gnu-syntax] [--relax] [--no-predefined-symbols]
171 [--no-expand] [--no-merge-gregs] [-x]
172 [--linker-allocated-gregs]
173 Target Nios II options:
175 [-relax-all] [-relax-section] [-no-relax]
176 [-EB] [-EL]
177 Target NDS32 options:
179 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
180 [-misa=isa] [-mabi=abi] [-mall-ext]
181 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
182 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
183 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
184 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
185 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
186 [-mb2bb]
187 Target PDP11 options:
189 [-mpic|-mno-pic] [-mall] [-mno-extensions]
190 [-mextension|-mno-extension]
191 [-mcpu] [-mmachine]
192 Target picoJava options:
194 [-mb|-me]
195 Target PowerPC options:
197 [-a32|-a64]
198 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
199 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
200 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
201 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
202 -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
203 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
204 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
205 [-mregnames|-mno-regnames]
206 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
207 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
208 [-msolaris|-mno-solaris]
209 [-nops=count]
210 Target PRU options:
212 [-link-relax]
213 [-mnolink-relax]
214 [-mno-warn-regname-label]
215 Target RISC-V options:
217 [-fpic|-fPIC|-fno-pic]
218 [-march=ISA]
219 [-mabi=ABI]
220 Target RL78 options:
222 [-mg10]
223 [-m32bit-doubles|-m64bit-doubles]
224 Target RX options:
226 [-mlittle-endian|-mbig-endian]
227 [-m32bit-doubles|-m64bit-doubles]
228 [-muse-conventional-section-names]
229 [-msmall-data-limit]
230 [-mpid]
231 [-mrelax]
232 [-mint-register=number]
233 [-mgcc-abi|-mrx-abi]
234 Target s390 options:
236 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
237 [-mregnames|-mno-regnames]
238 [-mwarn-areg-zero]
239 Target SCORE options:
241 [-EB][-EL][-FIXDD][-NWARN]
242 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
243 [-march=score7][-march=score3]
244 [-USE_R1][-KPIC][-O0][-G num][-V]
245 Target SPARC options:
247 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
248 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
249 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
250 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
251 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
252 -Asparcvisr|-Asparc5]
253 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
254 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
255 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
256 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
257 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
258 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
259 -bump]
260 [-32|-64]
261 [--enforce-aligned-data][--dcti-couples-detect]
262 Target TIC54X options:
264 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
265 [-merrors-to-file <filename>|-me <filename>]
266 Target TIC6X options:
268 [-march=arch] [-mbig-endian|-mlittle-endian]
269 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
270 [-mpic|-mno-pic]
271 Target TILE-Gx options:
273 [-m32|-m64][-EB][-EL]
274 Target Visium options:
276 [-mtune=arch]
277 Target Xtensa options:
279 [--[no-]text-section-literals] [--[no-]auto-litpools]
280 [--[no-]absolute-literals]
281 [--[no-]target-align] [--[no-]longcalls]
282 [--[no-]transform]
283 [--rename-section oldname=newname]
284 [--[no-]trampolines]
285 Target Z80 options:
287 [-z80] [-r800]
288 [ -ignore-undocumented-instructions] [-Wnud]
289 [ -ignore-unportable-instructions] [-Wnup]
290 [ -warn-undocumented-instructions] [-Wud]
291 [ -warn-unportable-instructions] [-Wup]
292 [ -forbid-undocumented-instructions] [-Fud]
293 [ -forbid-unportable-instructions] [-Fup]
294
296 GNU as is really a family of assemblers. If you use (or have used) the
297 GNU assembler on one architecture, you should find a fairly similar
298 environment when you use it on another architecture. Each version has
299 much in common with the others, including object file formats, most
300 assembler directives (often called pseudo-ops) and assembler syntax.
301 as is primarily intended to assemble the output of the GNU C compiler
303 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
304 assemble correctly everything that other assemblers for the same
305 machine would assemble. Any exceptions are documented explicitly.
306 This doesn't mean as always uses the same syntax as another assembler
307 for the same architecture; for example, we know of several incompatible
308 versions of 680x0 assembly language syntax.
309 Each time you run as it assembles exactly one source program. The
311 source program is made up of one or more files. (The standard input is
312 also a file.)
313 You give as a command line that has zero or more input file names. The
315 input files are read (from left file name to right). A command line
316 argument (in any position) that has no special meaning is taken to be
317 an input file name.
318 If you give as no file names it attempts to read one input file from
320 the as standard input, which is normally your terminal. You may have
321 to type ctl-D to tell as there is no more program to assemble.
322 Use -- if you need to explicitly name the standard input file in your
324 command line.
325 If the source is empty, as produces a small, empty object file.
327 as may write warnings and error messages to the standard error file
329 (usually your terminal). This should not happen when a compiler runs
330 as automatically. Warnings report an assumption made so that as could
331 keep assembling a flawed program; errors report a grave problem that
332 stops the assembly.
333 If you are invoking as via the GNU C compiler, you can use the -Wa
335 option to pass arguments through to the assembler. The assembler
336 arguments must be separated from each other (and the -Wa) by commas.
337 For example:
338 gcc -c -g -O -Wa,-alh,-L file.c
340 This passes two options to the assembler: -alh (emit a listing to
342 standard output with high-level and assembly source) and -L (retain
343 local symbols in the symbol table).
344 Usually you do not need to use this -Wa mechanism, since many compiler
346 command-line options are automatically passed to the assembler by the
347 compiler. (You can call the GNU compiler driver with the -v option to
348 see precisely what options it passes to each compilation pass,
349 including the assembler.)
350
352 @file
353 Read command-line options from file. The options read are inserted
354 in place of the original @file option. If file does not exist, or
355 cannot be read, then the option will be treated literally, and not
356 removed.
357 Options in file are separated by whitespace. A whitespace
359 character may be included in an option by surrounding the entire
360 option in either single or double quotes. Any character (including
361 a backslash) may be included by prefixing the character to be
362 included with a backslash. The file may itself contain additional
363 @file options; any such options will be processed recursively.
364 -a[cdghlmns]
366 Turn on listings, in any of a variety of ways:
367 -ac omit false conditionals
369 -ad omit debugging directives
371 -ag include general information, like as version and options passed
373 -ah include high-level source
375 -al include assembly
377 -am include macro expansions
379 -an omit forms processing
381 -as include symbols
383 =file
385 set the name of the listing file
386 You may combine these options; for example, use -aln for assembly
388 listing without forms processing. The =file option, if used, must
389 be the last one. By itself, -a defaults to -ahls.
390 --alternate
392 Begin in alternate macro mode.
393 --compress-debug-sections
395 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
396 the ELF ABI. The resulting object file may not be compatible with
397 older linkers and object file utilities. Note if compression would
398 make a given section larger then it is not compressed.
399 --compress-debug-sections=none
401 --compress-debug-sections=zlib
402 --compress-debug-sections=zlib-gnu
403 --compress-debug-sections=zlib-gabi
404 These options control how DWARF debug sections are compressed.
405 --compress-debug-sections=none is equivalent to
406 --nocompress-debug-sections. --compress-debug-sections=zlib and
407 --compress-debug-sections=zlib-gabi are equivalent to
408 --compress-debug-sections. --compress-debug-sections=zlib-gnu
409 compresses DWARF debug sections using zlib. The debug sections are
410 renamed to begin with .zdebug. Note if compression would make a
411 given section larger then it is not compressed nor renamed.
412 --nocompress-debug-sections
414 Do not compress DWARF debug sections. This is usually the default
415 for all targets except the x86/x86_64, but a configure time option
416 can be used to override this.
417 -D Ignored. This option is accepted for script compatibility with
419 calls to other assemblers.
420 --debug-prefix-map old=new
422 When assembling files in directory old, record debugging
423 information describing them as in new instead.
424 --defsym sym=value
426 Define the symbol sym to be value before assembling the input file.
427 value must be an integer constant. As in C, a leading 0x indicates
428 a hexadecimal value, and a leading 0 indicates an octal value. The
429 value of the symbol can be overridden inside a source file via the
430 use of a ".set" pseudo-op.
431 -f "fast"---skip whitespace and comment preprocessing (assume source
433 is compiler output).
434 -g
436 --gen-debug
437 Generate debugging information for each assembler source line using
438 whichever debug format is preferred by the target. This currently
439 means either STABS, ECOFF or DWARF2.
440 --gstabs
442 Generate stabs debugging information for each assembler line. This
443 may help debugging assembler code, if the debugger can handle it.
444 --gstabs+
446 Generate stabs debugging information for each assembler line, with
447 GNU extensions that probably only gdb can handle, and that could
448 make other debuggers crash or refuse to read your program. This
449 may help debugging assembler code. Currently the only GNU
450 extension is the location of the current working directory at
451 assembling time.
452 --gdwarf-2
454 Generate DWARF2 debugging information for each assembler line.
455 This may help debugging assembler code, if the debugger can handle
456 it. Note---this option is only supported by some targets, not all
457 of them.
458 --gdwarf-sections
460 Instead of creating a .debug_line section, create a series of
461 .debug_line.foo sections where foo is the name of the corresponding
462 code section. For example a code section called .text.func will
463 have its dwarf line number information placed into a section called
464 .debug_line.text.func. If the code section is just called .text
465 then debug line section will still be called just .debug_line
466 without any suffix.
467 --size-check=error
469 --size-check=warning
470 Issue an error or warning for invalid ELF .size directive.
471 --elf-stt-common=no
473 --elf-stt-common=yes
474 These options control whether the ELF assembler should generate
475 common symbols with the "STT_COMMON" type. The default can be
476 controlled by a configure option --enable-elf-stt-common.
477 --help
479 Print a summary of the command line options and exit.
480 --target-help
482 Print a summary of all target specific options and exit.
483 -I dir
485 Add directory dir to the search list for ".include" directives.
486 -J Don't warn about signed overflow.
488 -K Issue warnings when difference tables altered for long
490 displacements.
491 -L
493 --keep-locals
494 Keep (in the symbol table) local symbols. These symbols start with
495 system-specific local label prefixes, typically .L for ELF systems
496 or L for traditional a.out systems.
497 --listing-lhs-width=number
499 Set the maximum width, in words, of the output data column for an
500 assembler listing to number.
501 --listing-lhs-width2=number
503 Set the maximum width, in words, of the output data column for
504 continuation lines in an assembler listing to number.
505 --listing-rhs-width=number
507 Set the maximum width of an input source line, as displayed in a
508 listing, to number bytes.
509 --listing-cont-lines=number
511 Set the maximum number of lines printed in a listing for a single
512 line of input to number + 1.
513 --no-pad-sections
515 Stop the assembler for padding the ends of output sections to the
516 alignment of that section. The default is to pad the sections, but
517 this can waste space which might be needed on targets which have
518 tight memory constraints.
519 -o objfile
521 Name the object-file output from as objfile.
522 -R Fold the data section into the text section.
524 --hash-size=number
526 Set the default size of GAS's hash tables to a prime number close
527 to number. Increasing this value can reduce the length of time it
528 takes the assembler to perform its tasks, at the expense of
529 increasing the assembler's memory requirements. Similarly reducing
530 this value can reduce the memory requirements at the expense of
531 speed.
532 --reduce-memory-overheads
534 This option reduces GAS's memory requirements, at the expense of
535 making the assembly processes slower. Currently this switch is a
536 synonym for --hash-size=4051, but in the future it may have other
537 effects as well.
538 --sectname-subst
540 Honor substitution sequences in section names.
541 --statistics
543 Print the maximum space (in bytes) and total time (in seconds) used
544 by assembly.
545 --strip-local-absolute
547 Remove local absolute symbols from the outgoing symbol table.
548 -v
550 -version
551 Print the as version.
552 --version
554 Print the as version and exit.
555 -W
557 --no-warn
558 Suppress warning messages.
559 --fatal-warnings
561 Treat warnings as errors.
562 --warn
564 Don't suppress warning messages or treat them as errors.
565 -w Ignored.
567 -x Ignored.
569 -Z Generate an object file even after errors.
571 -- | files ...
573 Standard input, or source files to assemble.
574 The following options are available when as is configured for the
576 64-bit mode of the ARM Architecture (AArch64).
577 -EB This option specifies that the output generated by the assembler
579 should be marked as being encoded for a big-endian processor.
580 -EL This option specifies that the output generated by the assembler
582 should be marked as being encoded for a little-endian processor.
583 -mabi=abi
585 Specify which ABI the source code uses. The recognized arguments
586 are: "ilp32" and "lp64", which decides the generated object file in
587 ELF32 and ELF64 format respectively. The default is "lp64".
588 -mcpu=processor[+extension...]
590 This option specifies the target processor. The assembler will
591 issue an error message if an attempt is made to assemble an
592 instruction which will not execute on the target processor. The
593 following processor names are recognized: "cortex-a35",
594 "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a72",
595 "cortex-a73", "cortex-a75", "exynos-m1", "falkor", "qdf24xx",
596 "saphira", "thunderx", "vulcan", "xgene1" and "xgene2". The
597 special name "all" may be used to allow the assembler to accept
598 instructions valid for any supported processor, including all
599 optional extensions.
600 In addition to the basic instruction set, the assembler can be told
602 to accept, or restrict, various extension mnemonics that extend the
603 processor.
604 If some implementations of a particular processor can have an
606 extension, then then those extensions are automatically enabled.
607 Consequently, you will not normally have to specify any additional
608 extensions.
609 -march=architecture[+extension...]
611 This option specifies the target architecture. The assembler will
612 issue an error message if an attempt is made to assemble an
613 instruction which will not execute on the target architecture. The
614 following architecture names are recognized: "armv8-a",
615 "armv8.1-a", "armv8.2-a", "armv8.3-a" and "armv8.4-a".
616 If both -mcpu and -march are specified, the assembler will use the
618 setting for -mcpu. If neither are specified, the assembler will
619 default to -mcpu=all.
620 The architecture option can be extended with the same instruction
622 set extension options as the -mcpu option. Unlike -mcpu,
623 extensions are not always enabled by default,
624 -mverbose-error
626 This option enables verbose error messages for AArch64 gas. This
627 option is enabled by default.
628 -mno-verbose-error
630 This option disables verbose error messages in AArch64 gas.
631 The following options are available when as is configured for an Alpha
633 processor.
634 -mcpu
636 This option specifies the target processor. If an attempt is made
637 to assemble an instruction which will not execute on the target
638 processor, the assembler may either expand the instruction as a
639 macro or issue an error message. This option is equivalent to the
640 ".arch" directive.
641 The following processor names are recognized: 21064, "21064a",
643 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
644 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
645 "ev67", "ev68". The special name "all" may be used to allow the
646 assembler to accept instructions valid for any Alpha processor.
647 In order to support existing practice in OSF/1 with respect to
649 ".arch", and existing practice within MILO (the Linux ARC
650 bootloader), the numbered processor names (e.g. 21064) enable the
651 processor-specific PALcode instructions, while the "electro-vlasic"
652 names (e.g. "ev4") do not.
653 -mdebug
655 -no-mdebug
656 Enables or disables the generation of ".mdebug" encapsulation for
657 stabs directives and procedure descriptors. The default is to
658 automatically enable ".mdebug" when the first stabs directive is
659 seen.
660 -relax
662 This option forces all relocations to be put into the object file,
663 instead of saving space and resolving some relocations at assembly
664 time. Note that this option does not propagate all symbol
665 arithmetic into the object file, because not all symbol arithmetic
666 can be represented. However, the option can still be useful in
667 specific applications.
668 -replace
670 -noreplace
671 Enables or disables the optimization of procedure calls, both at
672 assemblage and at link time. These options are only available for
673 VMS targets and "-replace" is the default. See section 1.4.1 of
674 the OpenVMS Linker Utility Manual.
675 -g This option is used when the compiler generates debug information.
677 When gcc is using mips-tfile to generate debug information for
678 ECOFF, local labels must be passed through to the object file.
679 Otherwise this option has no effect.
680 -Gsize
682 A local common symbol larger than size is placed in ".bss", while
683 smaller symbols are placed in ".sbss".
684 -F
686 -32addr
687 These options are ignored for backward compatibility.
688 The following options are available when as is configured for an ARC
690 processor.
691 -mcpu=cpu
693 This option selects the core processor variant.
694 -EB | -EL
696 Select either big-endian (-EB) or little-endian (-EL) output.
697 -mcode-density
699 Enable Code Density extenssion instructions.
700 The following options are available when as is configured for the ARM
702 processor family.
703 -mcpu=processor[+extension...]
705 Specify which ARM processor variant is the target.
706 -march=architecture[+extension...]
708 Specify which ARM architecture variant is used by the target.
709 -mfpu=floating-point-format
711 Select which Floating Point architecture is the target.
712 -mfloat-abi=abi
714 Select which floating point ABI is in use.
715 -mthumb
717 Enable Thumb only instruction decoding.
718 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
720 Select which procedure calling convention is in use.
721 -EB | -EL
723 Select either big-endian (-EB) or little-endian (-EL) output.
724 -mthumb-interwork
726 Specify that the code has been generated with interworking between
727 Thumb and ARM code in mind.
728 -mccs
730 Turns on CodeComposer Studio assembly syntax compatibility mode.
731 -k Specify that PIC code has been generated.
733 The following options are available when as is configured for the
735 Blackfin processor family.
736 -mcpu=processor[-sirevision]
738 This option specifies the target processor. The optional
739 sirevision is not used in assembler. It's here such that GCC can
740 easily pass down its "-mcpu=" option. The assembler will issue an
741 error message if an attempt is made to assemble an instruction
742 which will not execute on the target processor. The following
743 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
744 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
745 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
746 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
747 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
748 "bf549", "bf549m", "bf561", and "bf592".
749 -mfdpic
751 Assemble for the FDPIC ABI.
752 -mno-fdpic
754 -mnopic
755 Disable -mfdpic.
756 See the info pages for documentation of the CRIS-specific options.
758 The following options are available when as is configured for a D10V
760 processor.
761 -O Optimize output by parallelizing instructions.
763 The following options are available when as is configured for a D30V
765 processor.
766 -O Optimize output by parallelizing instructions.
768 -n Warn when nops are generated.
770 -N Warn when a nop after a 32-bit multiply instruction is generated.
772 The following options are available when as is configured for an
774 Epiphany processor.
775 -mepiphany
777 Specifies that the both 32 and 16 bit instructions are allowed.
778 This is the default behavior.
779 -mepiphany16
781 Restricts the permitted instructions to just the 16 bit set.
782 The following options are available when as is configured for an H8/300
784 processor. @chapter H8/300 Dependent Features
785 Options
787 The Renesas H8/300 version of "as" has one machine-dependent option:
788 -h-tick-hex
790 Support H'00 style hex constants in addition to 0x00 style.
791 -mach=name
793 Sets the H8300 machine variant. The following machine names are
794 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
795 "h8300sxn".
796 The following options are available when as is configured for an i386
798 processor.
799 --32 | --x32 | --64
801 Select the word size, either 32 bits or 64 bits. --32 implies
802 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
803 architecture with 32-bit or 64-bit word-size respectively.
804 These options are only available with the ELF object file format,
806 and require that the necessary BFD support has been included (on a
807 32-bit platform you have to add --enable-64-bit-bfd to configure
808 enable 64-bit usage and use x86-64 as target platform).
809 -n By default, x86 GAS replaces multiple nop instructions used for
811 alignment within code sections with multi-byte nop instructions
812 such as leal 0(%esi,1),%esi. This switch disables the optimization
813 if a single byte nop (0x90) is explicitly specified as the fill
814 byte for alignment.
815 --divide
817 On SVR4-derived platforms, the character / is treated as a comment
818 character, which means that it cannot be used in expressions. The
819 --divide option turns / into a normal character. This does not
820 disable / at the beginning of a line starting a comment, or affect
821 using # for starting a comment.
822 -march=CPU[+EXTENSION...]
824 This option specifies the target processor. The assembler will
825 issue an error message if an attempt is made to assemble an
826 instruction which will not execute on the target processor. The
827 following processor names are recognized: "i8086", "i186", "i286",
828 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
829 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
830 "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
831 "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
832 "bdver3", "bdver4", "znver1", "btver1", "btver2", "generic32" and
833 "generic64".
834 In addition to the basic instruction set, the assembler can be told
836 to accept various extension mnemonics. For example,
837 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
838 following extensions are currently supported: 8087, 287, 387, 687,
839 "no87", "no287", "no387", "no687", "mmx", "nommx", "sse", "sse2",
840 "sse3", "ssse3", "sse4.1", "sse4.2", "sse4", "nosse", "nosse2",
841 "nosse3", "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx",
842 "avx2", "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap",
843 "mpx", "sha", "rdpid", "ptwrite", "cet", "gfni", "vaes",
844 "vpclmulqdq", "prefetchwt1", "clflushopt", "se1", "clwb",
845 "avx512f", "avx512cd", "avx512er", "avx512pf", "avx512vl",
846 "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi",
847 "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
848 "avx512_vbmi2", "avx512_vnni", "avx512_bitalg", "noavx512f",
849 "noavx512cd", "noavx512er", "noavx512pf", "noavx512vl",
850 "noavx512bw", "noavx512dq", "noavx512ifma", "noavx512vbmi",
851 "noavx512_4fmaps", "noavx512_4vnniw", "noavx512_vpopcntdq",
852 "noavx512_vbmi2", "noavx512_vnni", "noavx512_bitalg", "vmx",
853 "vmfunc", "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes",
854 "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe",
855 "ept", "lzcnt", "hle", "rtm", "invpcid", "clflush", "mwaitx",
856 "clzero", "lwp", "fma4", "xop", "cx16", "syscall", "rdtscp",
857 "3dnow", "3dnowa", "sse4a", "sse5", "svme", "abm" and "padlock".
858 Note that rather than extending a basic instruction set, the
859 extension mnemonics starting with "no" revoke the respective
860 functionality.
861 When the ".arch" directive is used with -march, the ".arch"
863 directive will take precedent.
864 -mtune=CPU
866 This option specifies a processor to optimize for. When used in
867 conjunction with the -march option, only instructions of the
868 processor specified by the -march option will be generated.
869 Valid CPU values are identical to the processor list of -march=CPU.
871 -msse2avx
873 This option specifies that the assembler should encode SSE
874 instructions with VEX prefix.
875 -msse-check=none
877 -msse-check=warning
878 -msse-check=error
879 These options control if the assembler should check SSE
880 instructions. -msse-check=none will make the assembler not to
881 check SSE instructions, which is the default. -msse-check=warning
882 will make the assembler issue a warning for any SSE instruction.
883 -msse-check=error will make the assembler issue an error for any
884 SSE instruction.
885 -mavxscalar=128
887 -mavxscalar=256
888 These options control how the assembler should encode scalar AVX
889 instructions. -mavxscalar=128 will encode scalar AVX instructions
890 with 128bit vector length, which is the default. -mavxscalar=256
891 will encode scalar AVX instructions with 256bit vector length.
892 -mevexlig=128
894 -mevexlig=256
895 -mevexlig=512
896 These options control how the assembler should encode length-
897 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
898 EVEX instructions with 128bit vector length, which is the default.
899 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
900 with 256bit and 512bit vector length, respectively.
901 -mevexwig=0
903 -mevexwig=1
904 These options control how the assembler should encode w-ignored
905 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
906 instructions with evex.w = 0, which is the default. -mevexwig=1
907 will encode WIG EVEX instructions with evex.w = 1.
908 -mmnemonic=att
910 -mmnemonic=intel
911 This option specifies instruction mnemonic for matching
912 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
913 will take precedent.
914 -msyntax=att
916 -msyntax=intel
917 This option specifies instruction syntax when processing
918 instructions. The ".att_syntax" and ".intel_syntax" directives
919 will take precedent.
920 -mnaked-reg
922 This option specifies that registers don't require a % prefix. The
923 ".att_syntax" and ".intel_syntax" directives will take precedent.
924 -madd-bnd-prefix
926 This option forces the assembler to add BND prefix to all branches,
927 even if such prefix was not explicitly specified in the source
928 code.
929 -mno-shared
931 On ELF target, the assembler normally optimizes out non-PLT
932 relocations against defined non-weak global branch targets with
933 default visibility. The -mshared option tells the assembler to
934 generate code which may go into a shared library where all non-weak
935 global branch targets with default visibility can be preempted.
936 The resulting code is slightly bigger. This option only affects
937 the handling of branch instructions.
938 -mbig-obj
940 On x86-64 PE/COFF target this option forces the use of big object
941 file format, which allows more than 32768 sections.
942 -momit-lock-prefix=no
944 -momit-lock-prefix=yes
945 These options control how the assembler should encode lock prefix.
946 This option is intended as a workaround for processors, that fail
947 on lock prefix. This option can only be safely used with single-
948 core, single-thread computers -momit-lock-prefix=yes will omit all
949 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
950 usual, which is the default.
951 -mfence-as-lock-add=no
953 -mfence-as-lock-add=yes
954 These options control how the assembler should encode lfence,
955 mfence and sfence. -mfence-as-lock-add=yes will encode lfence,
956 mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
957 addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will
958 encode lfence, mfence and sfence as usual, which is the default.
959 -mrelax-relocations=no
961 -mrelax-relocations=yes
962 These options control whether the assembler should generate relax
963 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
964 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
965 -mrelax-relocations=yes will generate relax relocations.
966 -mrelax-relocations=no will not generate relax relocations. The
967 default can be controlled by a configure option
968 --enable-x86-relax-relocations.
969 -mevexrcig=rne
971 -mevexrcig=rd
972 -mevexrcig=ru
973 -mevexrcig=rz
974 These options control how the assembler should encode SAE-only EVEX
975 instructions. -mevexrcig=rne will encode RC bits of EVEX
976 instruction with 00, which is the default. -mevexrcig=rd,
977 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
978 instructions with 01, 10 and 11 RC bits, respectively.
979 -mamd64
981 -mintel64
982 This option specifies that the assembler should accept only AMD64
983 or Intel64 ISA in 64-bit mode. The default is to accept both.
984 The following options are available when as is configured for the Intel
986 80960 processor.
987 -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
989 Specify which variant of the 960 architecture is the target.
990 -b Add code to collect statistics about branches taken.
992 -no-relax
994 Do not alter compare-and-branch instructions for long
995 displacements; error if necessary.
996 The following options are available when as is configured for the
998 Ubicom IP2K series.
999 -mip2022ext
1001 Specifies that the extended IP2022 instructions are allowed.
1002 -mip2022
1004 Restores the default behaviour, which restricts the permitted
1005 instructions to just the basic IP2022 ones.
1006 The following options are available when as is configured for the
1008 Renesas M32C and M16C processors.
1009 -m32c
1011 Assemble M32C instructions.
1012 -m16c
1014 Assemble M16C instructions (the default).
1015 -relax
1017 Enable support for link-time relaxations.
1018 -h-tick-hex
1020 Support H'00 style hex constants in addition to 0x00 style.
1021 The following options are available when as is configured for the
1023 Renesas M32R (formerly Mitsubishi M32R) series.
1024 --m32rx
1026 Specify which processor in the M32R family is the target. The
1027 default is normally the M32R, but this option changes it to the
1028 M32RX.
1029 --warn-explicit-parallel-conflicts or --Wp
1031 Produce warning messages when questionable parallel constructs are
1032 encountered.
1033 --no-warn-explicit-parallel-conflicts or --Wnp
1035 Do not produce warning messages when questionable parallel
1036 constructs are encountered.
1037 The following options are available when as is configured for the
1039 Motorola 68000 series.
1040 -l Shorten references to undefined symbols, to one word instead of
1042 two.
1043 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1045 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1046 | -m68333 | -m68340 | -mcpu32 | -m5200
1047 Specify what processor in the 68000 family is the target. The
1048 default is normally the 68020, but this can be changed at
1049 configuration time.
1050 -m68881 | -m68882 | -mno-68881 | -mno-68882
1052 The target machine does (or does not) have a floating-point
1053 coprocessor. The default is to assume a coprocessor for 68020,
1054 68030, and cpu32. Although the basic 68000 is not compatible with
1055 the 68881, a combination of the two can be specified, since it's
1056 possible to do emulation of the coprocessor instructions with the
1057 main processor.
1058 -m68851 | -mno-68851
1060 The target machine does (or does not) have a memory-management unit
1061 coprocessor. The default is to assume an MMU for 68020 and up.
1062 The following options are available when as is configured for an Altera
1064 Nios II processor.
1065 -relax-section
1067 Replace identified out-of-range branches with PC-relative "jmp"
1068 sequences when possible. The generated code sequences are suitable
1069 for use in position-independent code, but there is a practical
1070 limit on the extended branch range because of the length of the
1071 sequences. This option is the default.
1072 -relax-all
1074 Replace branch instructions not determinable to be in range and all
1075 call instructions with "jmp" and "callr" sequences (respectively).
1076 This option generates absolute relocations against the target
1077 symbols and is not appropriate for position-independent code.
1078 -no-relax
1080 Do not replace any branches or calls.
1081 -EB Generate big-endian output.
1083 -EL Generate little-endian output. This is the default.
1085 -march=architecture
1087 This option specifies the target architecture. The assembler
1088 issues an error message if an attempt is made to assemble an
1089 instruction which will not execute on the target architecture. The
1090 following architecture names are recognized: "r1", "r2". The
1091 default is "r1".
1092 The following options are available when as is configured for a PRU
1094 processor.
1095 -mlink-relax
1097 Assume that LD would optimize LDI32 instructions by checking the
1098 upper 16 bits of the expression. If they are all zeros, then LD
1099 would shorten the LDI32 instruction to a single LDI. In such case
1100 "as" will output DIFF relocations for diff expressions.
1101 -mno-link-relax
1103 Assume that LD would not optimize LDI32 instructions. As a
1104 consequence, DIFF relocations will not be emitted.
1105 -mno-warn-regname-label
1107 Do not warn if a label name matches a register name. Usually
1108 assembler programmers will want this warning to be emitted. C
1109 compilers may want to turn this off.
1110 The following options are available when as is configured for a MIPS
1112 processor.
1113 -G num
1115 This option sets the largest size of an object that can be
1116 referenced implicitly with the "gp" register. It is only accepted
1117 for targets that use ECOFF format, such as a DECstation running
1118 Ultrix. The default value is 8.
1119 -EB Generate "big endian" format output.
1121 -EL Generate "little endian" format output.
1123 -mips1
1125 -mips2
1126 -mips3
1127 -mips4
1128 -mips5
1129 -mips32
1130 -mips32r2
1131 -mips32r3
1132 -mips32r5
1133 -mips32r6
1134 -mips64
1135 -mips64r2
1136 -mips64r3
1137 -mips64r5
1138 -mips64r6
1139 Generate code for a particular MIPS Instruction Set Architecture
1140 level. -mips1 is an alias for -march=r3000, -mips2 is an alias for
1141 -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1142 alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3,
1143 -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1144 -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1145 MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1146 MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1147 Release 6 ISA processors, respectively.
1148 -march=cpu
1150 Generate code for a particular MIPS CPU.
1151 -mtune=cpu
1153 Schedule and tune for a particular MIPS CPU.
1154 -mfix7000
1156 -mno-fix7000
1157 Cause nops to be inserted if the read of the destination register
1158 of an mfhi or mflo instruction occurs in the following two
1159 instructions.
1160 -mfix-rm7000
1162 -mno-fix-rm7000
1163 Cause nops to be inserted if a dmult or dmultu instruction is
1164 followed by a load instruction.
1165 -mdebug
1167 -no-mdebug
1168 Cause stabs-style debugging output to go into an ECOFF-style
1169 .mdebug section instead of the standard ELF .stabs sections.
1170 -mpdr
1172 -mno-pdr
1173 Control generation of ".pdr" sections.
1174 -mgp32
1176 -mfp32
1177 The register sizes are normally inferred from the ISA and ABI, but
1178 these flags force a certain group of registers to be treated as 32
1179 bits wide at all times. -mgp32 controls the size of general-
1180 purpose registers and -mfp32 controls the size of floating-point
1181 registers.
1182 -mgp64
1184 -mfp64
1185 The register sizes are normally inferred from the ISA and ABI, but
1186 these flags force a certain group of registers to be treated as 64
1187 bits wide at all times. -mgp64 controls the size of general-
1188 purpose registers and -mfp64 controls the size of floating-point
1189 registers.
1190 -mfpxx
1192 The register sizes are normally inferred from the ISA and ABI, but
1193 using this flag in combination with -mabi=32 enables an ABI variant
1194 which will operate correctly with floating-point registers which
1195 are 32 or 64 bits wide.
1196 -modd-spreg
1198 -mno-odd-spreg
1199 Enable use of floating-point operations on odd-numbered single-
1200 precision registers when supported by the ISA. -mfpxx implies
1201 -mno-odd-spreg, otherwise the default is -modd-spreg.
1202 -mips16
1204 -no-mips16
1205 Generate code for the MIPS 16 processor. This is equivalent to
1206 putting ".module mips16" at the start of the assembly file.
1207 -no-mips16 turns off this option.
1208 -mmips16e2
1210 -mno-mips16e2
1211 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1212 equivalent to putting ".module mips16e2" at the start of the
1213 assembly file. -mno-mips16e2 turns off this option.
1214 -mmicromips
1216 -mno-micromips
1217 Generate code for the microMIPS processor. This is equivalent to
1218 putting ".module micromips" at the start of the assembly file.
1219 -mno-micromips turns off this option. This is equivalent to
1220 putting ".module nomicromips" at the start of the assembly file.
1221 -msmartmips
1223 -mno-smartmips
1224 Enables the SmartMIPS extension to the MIPS32 instruction set.
1225 This is equivalent to putting ".module smartmips" at the start of
1226 the assembly file. -mno-smartmips turns off this option.
1227 -mips3d
1229 -no-mips3d
1230 Generate code for the MIPS-3D Application Specific Extension. This
1231 tells the assembler to accept MIPS-3D instructions. -no-mips3d
1232 turns off this option.
1233 -mdmx
1235 -no-mdmx
1236 Generate code for the MDMX Application Specific Extension. This
1237 tells the assembler to accept MDMX instructions. -no-mdmx turns
1238 off this option.
1239 -mdsp
1241 -mno-dsp
1242 Generate code for the DSP Release 1 Application Specific Extension.
1243 This tells the assembler to accept DSP Release 1 instructions.
1244 -mno-dsp turns off this option.
1245 -mdspr2
1247 -mno-dspr2
1248 Generate code for the DSP Release 2 Application Specific Extension.
1249 This option implies -mdsp. This tells the assembler to accept DSP
1250 Release 2 instructions. -mno-dspr2 turns off this option.
1251 -mdspr3
1253 -mno-dspr3
1254 Generate code for the DSP Release 3 Application Specific Extension.
1255 This option implies -mdsp and -mdspr2. This tells the assembler to
1256 accept DSP Release 3 instructions. -mno-dspr3 turns off this
1257 option.
1258 -mmsa
1260 -mno-msa
1261 Generate code for the MIPS SIMD Architecture Extension. This tells
1262 the assembler to accept MSA instructions. -mno-msa turns off this
1263 option.
1264 -mxpa
1266 -mno-xpa
1267 Generate code for the MIPS eXtended Physical Address (XPA)
1268 Extension. This tells the assembler to accept XPA instructions.
1269 -mno-xpa turns off this option.
1270 -mmt
1272 -mno-mt
1273 Generate code for the MT Application Specific Extension. This
1274 tells the assembler to accept MT instructions. -mno-mt turns off
1275 this option.
1276 -mmcu
1278 -mno-mcu
1279 Generate code for the MCU Application Specific Extension. This
1280 tells the assembler to accept MCU instructions. -mno-mcu turns off
1281 this option.
1282 -minsn32
1284 -mno-insn32
1285 Only use 32-bit instruction encodings when generating code for the
1286 microMIPS processor. This option inhibits the use of any 16-bit
1287 instructions. This is equivalent to putting ".set insn32" at the
1288 start of the assembly file. -mno-insn32 turns off this option.
1289 This is equivalent to putting ".set noinsn32" at the start of the
1290 assembly file. By default -mno-insn32 is selected, allowing all
1291 instructions to be used.
1292 --construct-floats
1294 --no-construct-floats
1295 The --no-construct-floats option disables the construction of
1296 double width floating point constants by loading the two halves of
1297 the value into the two single width floating point registers that
1298 make up the double width register. By default --construct-floats
1299 is selected, allowing construction of these floating point
1300 constants.
1301 --relax-branch
1303 --no-relax-branch
1304 The --relax-branch option enables the relaxation of out-of-range
1305 branches. By default --no-relax-branch is selected, causing any
1306 out-of-range branches to produce an error.
1307 -mignore-branch-isa
1309 -mno-ignore-branch-isa
1310 Ignore branch checks for invalid transitions between ISA modes.
1311 The semantics of branches does not provide for an ISA mode switch,
1312 so in most cases the ISA mode a branch has been encoded for has to
1313 be the same as the ISA mode of the branch's target label.
1314 Therefore GAS has checks implemented that verify in branch assembly
1315 that the two ISA modes match. -mignore-branch-isa disables these
1316 checks. By default -mno-ignore-branch-isa is selected, causing any
1317 invalid branch requiring a transition between ISA modes to produce
1318 an error.
1319 -mnan=encoding
1321 Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1322 (-mnan=legacy) NaN encoding format. The latter is the default.
1323 --emulation=name
1325 This option was formerly used to switch between ELF and ECOFF
1326 output on targets like IRIX 5 that supported both. MIPS ECOFF
1327 support was removed in GAS 2.24, so the option now serves little
1328 purpose. It is retained for backwards compatibility.
1329 The available configuration names are: mipself, mipslelf and
1331 mipsbelf. Choosing mipself now has no effect, since the output is
1332 always ELF. mipslelf and mipsbelf select little- and big-endian
1333 output respectively, but -EL and -EB are now the preferred options
1334 instead.
1335 -nocpp
1337 as ignores this option. It is accepted for compatibility with the
1338 native tools.
1339 --trap
1341 --no-trap
1342 --break
1343 --no-break
1344 Control how to deal with multiplication overflow and division by
1345 zero. --trap or --no-break (which are synonyms) take a trap
1346 exception (and only work for Instruction Set Architecture level 2
1347 and higher); --break or --no-trap (also synonyms, and the default)
1348 take a break exception.
1349 -n When this option is used, as will issue a warning every time it
1351 generates a nop instruction from a macro.
1352 The following options are available when as is configured for a Meta
1354 processor.
1355 "-mcpu=metac11"
1357 Generate code for Meta 1.1.
1358 "-mcpu=metac12"
1360 Generate code for Meta 1.2.
1361 "-mcpu=metac21"
1363 Generate code for Meta 2.1.
1364 "-mfpu=metac21"
1366 Allow code to use FPU hardware of Meta 2.1.
1367 See the info pages for documentation of the MMIX-specific options.
1369 The following options are available when as is configured for a NDS32
1371 processor.
1372 "-O1"
1374 Optimize for performance.
1375 "-Os"
1377 Optimize for space.
1378 "-EL"
1380 Produce little endian data output.
1381 "-EB"
1383 Produce little endian data output.
1384 "-mpic"
1386 Generate PIC.
1387 "-mno-fp-as-gp-relax"
1389 Suppress fp-as-gp relaxation for this file.
1390 "-mb2bb-relax"
1392 Back-to-back branch optimization.
1393 "-mno-all-relax"
1395 Suppress all relaxation for this file.
1396 "-march=<arch name>"
1398 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1399 v3f, v3s, v2, v2j, v2f, v2s.
1400 "-mbaseline=<baseline>"
1402 Assemble for baseline <baseline> which could be v2, v3, v3m.
1403 "-mfpu-freg=FREG"
1405 Specify a FPU configuration.
1406 "0 8 SP / 4 DP registers"
1408 "1 16 SP / 8 DP registers"
1409 "2 32 SP / 16 DP registers"
1410 "3 32 SP / 32 DP registers"
1411 "-mabi=abi"
1412 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1413 "-m[no-]mac"
1415 Enable/Disable Multiply instructions support.
1416 "-m[no-]div"
1418 Enable/Disable Divide instructions support.
1419 "-m[no-]16bit-ext"
1421 Enable/Disable 16-bit extension
1422 "-m[no-]dx-regs"
1424 Enable/Disable d0/d1 registers
1425 "-m[no-]perf-ext"
1427 Enable/Disable Performance extension
1428 "-m[no-]perf2-ext"
1430 Enable/Disable Performance extension 2
1431 "-m[no-]string-ext"
1433 Enable/Disable String extension
1434 "-m[no-]reduced-regs"
1436 Enable/Disable Reduced Register configuration (GPR16) option
1437 "-m[no-]audio-isa-ext"
1439 Enable/Disable AUDIO ISA extension
1440 "-m[no-]fpu-sp-ext"
1442 Enable/Disable FPU SP extension
1443 "-m[no-]fpu-dp-ext"
1445 Enable/Disable FPU DP extension
1446 "-m[no-]fpu-fma"
1448 Enable/Disable FPU fused-multiply-add instructions
1449 "-mall-ext"
1451 Turn on all extensions and instructions support
1452 The following options are available when as is configured for a PowerPC
1454 processor.
1455 -a32
1457 Generate ELF32 or XCOFF32.
1458 -a64
1460 Generate ELF64 or XCOFF64.
1461 -K PIC
1463 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1464 -mpwrx | -mpwr2
1466 Generate code for POWER/2 (RIOS2).
1467 -mpwr
1469 Generate code for POWER (RIOS1)
1470 -m601
1472 Generate code for PowerPC 601.
1473 -mppc, -mppc32, -m603, -m604
1475 Generate code for PowerPC 603/604.
1476 -m403, -m405
1478 Generate code for PowerPC 403/405.
1479 -m440
1481 Generate code for PowerPC 440. BookE and some 405 instructions.
1482 -m464
1484 Generate code for PowerPC 464.
1485 -m476
1487 Generate code for PowerPC 476.
1488 -m7400, -m7410, -m7450, -m7455
1490 Generate code for PowerPC 7400/7410/7450/7455.
1491 -m750cl
1493 Generate code for PowerPC 750CL.
1494 -m821, -m850, -m860
1496 Generate code for PowerPC 821/850/860.
1497 -mppc64, -m620
1499 Generate code for PowerPC 620/625/630.
1500 -me500, -me500x2
1502 Generate code for Motorola e500 core complex.
1503 -me500mc
1505 Generate code for Freescale e500mc core complex.
1506 -me500mc64
1508 Generate code for Freescale e500mc64 core complex.
1509 -me5500
1511 Generate code for Freescale e5500 core complex.
1512 -me6500
1514 Generate code for Freescale e6500 core complex.
1515 -mspe
1517 Generate code for Motorola SPE instructions.
1518 -mspe2
1520 Generate code for Freescale SPE2 instructions.
1521 -mtitan
1523 Generate code for AppliedMicro Titan core complex.
1524 -mppc64bridge
1526 Generate code for PowerPC 64, including bridge insns.
1527 -mbooke
1529 Generate code for 32-bit BookE.
1530 -ma2
1532 Generate code for A2 architecture.
1533 -me300
1535 Generate code for PowerPC e300 family.
1536 -maltivec
1538 Generate code for processors with AltiVec instructions.
1539 -mvle
1541 Generate code for Freescale PowerPC VLE instructions.
1542 -mvsx
1544 Generate code for processors with Vector-Scalar (VSX) instructions.
1545 -mhtm
1547 Generate code for processors with Hardware Transactional Memory
1548 instructions.
1549 -mpower4, -mpwr4
1551 Generate code for Power4 architecture.
1552 -mpower5, -mpwr5, -mpwr5x
1554 Generate code for Power5 architecture.
1555 -mpower6, -mpwr6
1557 Generate code for Power6 architecture.
1558 -mpower7, -mpwr7
1560 Generate code for Power7 architecture.
1561 -mpower8, -mpwr8
1563 Generate code for Power8 architecture.
1564 -mpower9, -mpwr9
1566 Generate code for Power9 architecture.
1567 -mcell
1569 -mcell
1570 Generate code for Cell Broadband Engine architecture.
1571 -mcom
1573 Generate code Power/PowerPC common instructions.
1574 -many
1576 Generate code for any architecture (PWR/PWRX/PPC).
1577 -mregnames
1579 Allow symbolic names for registers.
1580 -mno-regnames
1582 Do not allow symbolic names for registers.
1583 -mrelocatable
1585 Support for GCC's -mrelocatable option.
1586 -mrelocatable-lib
1588 Support for GCC's -mrelocatable-lib option.
1589 -memb
1591 Set PPC_EMB bit in ELF flags.
1592 -mlittle, -mlittle-endian, -le
1594 Generate code for a little endian machine.
1595 -mbig, -mbig-endian, -be
1597 Generate code for a big endian machine.
1598 -msolaris
1600 Generate code for Solaris.
1601 -mno-solaris
1603 Do not generate code for Solaris.
1604 -nops=count
1606 If an alignment directive inserts more than count nops, put a
1607 branch at the beginning to skip execution of the nops.
1608 The following options are available when as is configured for a RISC-V
1610 processor.
1611 -fpic
1613 -fPIC
1614 Generate position-independent code
1615 -fno-pic
1617 Don't generate position-independent code (default)
1618 -march=ISA
1620 Select the base isa, as specified by ISA. For example
1621 -march=rv32ima.
1622 -mabi=ABI
1624 Selects the ABI, which is either "ilp32" or "lp64", optionally
1625 followed by "f", "d", or "q" to indicate single-precision, double-
1626 precision, or quad-precision floating-point calling convention, or
1627 none to indicate the soft-float calling convention.
1628 See the info pages for documentation of the RX-specific options.
1630 The following options are available when as is configured for the s390
1632 processor family.
1633 -m31
1635 -m64
1636 Select the word size, either 31/32 bits or 64 bits.
1637 -mesa
1639 -mzarch
1640 Select the architecture mode, either the Enterprise System
1641 Architecture (esa) or the z/Architecture mode (zarch).
1642 -march=processor
1644 Specify which s390 processor variant is the target, g5 (or arch3),
1645 g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
1646 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), or
1647 z14 (or arch12).
1648 -mregnames
1650 -mno-regnames
1651 Allow or disallow symbolic names for registers.
1652 -mwarn-areg-zero
1654 Warn whenever the operand for a base or index register has been
1655 specified but evaluates to zero.
1656 The following options are available when as is configured for a
1658 TMS320C6000 processor.
1659 -march=arch
1661 Enable (only) instructions from architecture arch. By default, all
1662 instructions are permitted.
1663 The following values of arch are accepted: "c62x", "c64x", "c64x+",
1665 "c67x", "c67x+", "c674x".
1666 -mdsbt
1668 -mno-dsbt
1669 The -mdsbt option causes the assembler to generate the
1670 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1671 code is using DSBT addressing. The -mno-dsbt option, the default,
1672 causes the tag to have a value of 0, indicating that the code does
1673 not use DSBT addressing. The linker will emit a warning if objects
1674 of different type (DSBT and non-DSBT) are linked together.
1675 -mpid=no
1677 -mpid=near
1678 -mpid=far
1679 The -mpid= option causes the assembler to generate the
1680 "Tag_ABI_PID" attribute with a value indicating the form of data
1681 addressing used by the code. -mpid=no, the default, indicates
1682 position-dependent data addressing, -mpid=near indicates position-
1683 independent addressing with GOT accesses using near DP addressing,
1684 and -mpid=far indicates position-independent addressing with GOT
1685 accesses using far DP addressing. The linker will emit a warning
1686 if objects built with different settings of this option are linked
1687 together.
1688 -mpic
1690 -mno-pic
1691 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1692 attribute with a value of 1, indicating that the code is using
1693 position-independent code addressing, The "-mno-pic" option, the
1694 default, causes the tag to have a value of 0, indicating position-
1695 dependent code addressing. The linker will emit a warning if
1696 objects of different type (position-dependent and position-
1697 independent) are linked together.
1698 -mbig-endian
1700 -mlittle-endian
1701 Generate code for the specified endianness. The default is little-
1702 endian.
1703 The following options are available when as is configured for a TILE-Gx
1705 processor.
1706 -m32 | -m64
1708 Select the word size, either 32 bits or 64 bits.
1709 -EB | -EL
1711 Select the endianness, either big-endian (-EB) or little-endian
1712 (-EL).
1713 The following option is available when as is configured for a Visium
1715 processor.
1716 -mtune=arch
1718 This option specifies the target architecture. If an attempt is
1719 made to assemble an instruction that will not execute on the target
1720 architecture, the assembler will issue an error message.
1721 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
1723 The following options are available when as is configured for an Xtensa
1725 processor.
1726 --text-section-literals | --no-text-section-literals
1728 Control the treatment of literal pools. The default is
1729 --no-text-section-literals, which places literals in separate
1730 sections in the output file. This allows the literal pool to be
1731 placed in a data RAM/ROM. With --text-section-literals, the
1732 literals are interspersed in the text section in order to keep them
1733 as close as possible to their references. This may be necessary
1734 for large assembly files, where the literals would otherwise be out
1735 of range of the "L32R" instructions in the text section. Literals
1736 are grouped into pools following ".literal_position" directives or
1737 preceding "ENTRY" instructions. These options only affect literals
1738 referenced via PC-relative "L32R" instructions; literals for
1739 absolute mode "L32R" instructions are handled separately.
1740 --auto-litpools | --no-auto-litpools
1742 Control the treatment of literal pools. The default is
1743 --no-auto-litpools, which in the absence of --text-section-literals
1744 places literals in separate sections in the output file. This
1745 allows the literal pool to be placed in a data RAM/ROM. With
1746 --auto-litpools, the literals are interspersed in the text section
1747 in order to keep them as close as possible to their references,
1748 explicit ".literal_position" directives are not required. This may
1749 be necessary for very large functions, where single literal pool at
1750 the beginning of the function may not be reachable by "L32R"
1751 instructions at the end. These options only affect literals
1752 referenced via PC-relative "L32R" instructions; literals for
1753 absolute mode "L32R" instructions are handled separately. When
1754 used together with --text-section-literals, --auto-litpools takes
1755 precedence.
1756 --absolute-literals | --no-absolute-literals
1758 Indicate to the assembler whether "L32R" instructions use absolute
1759 or PC-relative addressing. If the processor includes the absolute
1760 addressing option, the default is to use absolute "L32R"
1761 relocations. Otherwise, only the PC-relative "L32R" relocations
1762 can be used.
1763 --target-align | --no-target-align
1765 Enable or disable automatic alignment to reduce branch penalties at
1766 some expense in code size. This optimization is enabled by
1767 default. Note that the assembler will always align instructions
1768 like "LOOP" that have fixed alignment requirements.
1769 --longcalls | --no-longcalls
1771 Enable or disable transformation of call instructions to allow
1772 calls across a greater range of addresses. This option should be
1773 used when call targets can potentially be out of range. It may
1774 degrade both code size and performance, but the linker can
1775 generally optimize away the unnecessary overhead when a call ends
1776 up within range. The default is --no-longcalls.
1777 --transform | --no-transform
1779 Enable or disable all assembler transformations of Xtensa
1780 instructions, including both relaxation and optimization. The
1781 default is --transform; --no-transform should only be used in the
1782 rare cases when the instructions must be exactly as specified in
1783 the assembly source. Using --no-transform causes out of range
1784 instruction operands to be errors.
1785 --rename-section oldname=newname
1787 Rename the oldname section to newname. This option can be used
1788 multiple times to rename multiple sections.
1789 --trampolines | --no-trampolines
1791 Enable or disable transformation of jump instructions to allow
1792 jumps across a greater range of addresses. This option should be
1793 used when jump targets can potentially be out of range. In the
1794 absence of such jumps this option does not affect code size or
1795 performance. The default is --trampolines.
1796 The following options are available when as is configured for a Z80
1798 family processor.
1799 -z80
1801 Assemble for Z80 processor.
1802 -r800
1804 Assemble for R800 processor.
1805 -ignore-undocumented-instructions
1807 -Wnud
1808 Assemble undocumented Z80 instructions that also work on R800
1809 without warning.
1810 -ignore-unportable-instructions
1812 -Wnup
1813 Assemble all undocumented Z80 instructions without warning.
1814 -warn-undocumented-instructions
1816 -Wud
1817 Issue a warning for undocumented Z80 instructions that also work on
1818 R800.
1819 -warn-unportable-instructions
1821 -Wup
1822 Issue a warning for undocumented Z80 instructions that do not work
1823 on R800.
1824 -forbid-undocumented-instructions
1826 -Fud
1827 Treat all undocumented instructions as errors.
1828 -forbid-unportable-instructions
1830 -Fup
1831 Treat undocumented Z80 instructions that do not work on R800 as
1832 errors.
1833
1835 gcc(1), ld(1), and the Info entries for binutils and ld.
1836
1838 Copyright (c) 1991-2018 Free Software Foundation, Inc.
1839 Permission is granted to copy, distribute and/or modify this document
1841 under the terms of the GNU Free Documentation License, Version 1.3 or
1842 any later version published by the Free Software Foundation; with no
1843 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
1844 Texts. A copy of the license is included in the section entitled "GNU
1845 Free Documentation License".
1846binutils-2.30 2018-01-27 AS(1)