1PAT(5)                     cao-vlsi reference manual                    PAT(5)
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NAME

6       PAT - Pattern description format
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DESCRIPTION

10       The  pat is a specific format used in simulation pattern´s description.
11       pat format has been designed to represent undifferently patterns to  be
12       simulated or simulation's results. It offers the possibility of:
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15       specifying  the input list of the circuit: signals to be controled dur‐
16       ing the simulation by the user. For a circuit described  in  VHDL,  are
17       considered as input:
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19              external ports of the mode in.
20              guarded  external  ports  of  the  mode inout (declared with the
21              reserved word bus).
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24       specifying the output list of the circuit: signals to be observed  dur‐
25       ing  the simulation. For a circuit described in VHDL, are considered as
26       output:
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28              external ports of the mode out (declared either with or  without
29              the reserved word bus).
30              external  ports of the mode inout (declared either with or with‐
31              out the reserved word bus).
32              internal signals of a hierarchical description.
33              internal signals of a behavioural description (declared as  bus,
34              register or simple signal)
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37       specifying a read-write format for inputs and outputs.
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40       forcing the value of each input.
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43       checking the resulted value on each output.
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46       changing  the  value of an internal register (a guarded internal signal
47       of kind register in a behavioural description).
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50       saving the state of the circuit.
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THE FORMAT

54       A pattern file written in pat format can be divided into two parts: the
55       declaration  block  and  the  description  block. The instruction begin
56       marks the end of the declaration and the beginning of  the  description
57       block. The instruction end; marks the end of the file.
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60       The  declaration block is a set of input-output declaration statements.
61       The order of these declarations is important. In the description block,
62       values  will  be  associated with an input-output in the order of their
63       declaration.  That is, the first value  will  be  associated  with  the
64       first declared input-output and, the last value with the last one.
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67       A declaration statement has of one of the two following forms :
68              mode input_output_name [format] [spy_option];
69              mode group_name (input_output_name, ...) [format] [spy_option];
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72       The  second  form allows the user to give a name to a group of signals.
73       This group of signals will be called virtual array. Using this grouping
74       possibility,  great  care  must  be taken. Two guarded outputs (of kind
75       bus) can be grouped only if their  guard  expression  are  exactly  the
76       same.
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79       inputs    An  external  port  of  the mode in must be declared with the
80                 mode in. A guarded external port of the mode  inout  must  be
81                 declared with the mode inout.
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84       outputs   An  external  port  (guarded  or not) of the mode out must be
85                 declared with the mode out. An unguarded external port of the
86                 mode  inout  must  be  declared  with the mode out. A guarded
87                 external port of the mode inout must  be  declared  with  the
88                 mode  inout.  An  internal  signal (simple or guarded of kind
89                 bus) of a  behavioural  or  structural  description  must  be
90                 declared  with the mode signal. An internal register (guarded
91                 signal of kind register) is to be declared with  mode  regis‐
92                 ter.
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95       The  format  specifies the format under which values associated with an
96       input-output must be read or written. Legal formats are X for hexadeci‐
97       mal,  O  for  octal and, B for binary. The binary format is the default
98       format.
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101       The input_output_name is used to identify the input-output signal.  For
102       an  external  port,  the signal´s identifier added, if the signal is an
103       array, to its constraint (the  range  of  the  array)  constitutes  the
104       input-output  name.   For  an  internal signal the input_output_name is
105       made from the concatenation of the access_path and  the  signal´s  name
106       (identifier and if needed constraint). The access_path is a string rep‐
107       resenting the instance where the signal is declared. It is  a  list  of
108       instance names separated by ´.´ (dot).
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111       The  spy  option (keyword spy) may be used for outputs (out port, inout
112       port, internal signal). This option makes  one  additional  pattern  be
113       printed  in  the  result  file each time an event occurs on this signal
114       during the simulation and the corresponding pattern  (with  this  event
115       date) has been omitted in the input pattern file.
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118       Putting  one  or  several  additional  ´;´ (semicolon) at the end of an
119       input-output declaration makes one or several blank columns (up to  15)
120       be printed in the result file after the input-output's value.
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123       The  description  block  is a series of pattern description statements.
124       Each pattern is a list of values preceded by a date and optionally by a
125       label.
126              [date] [label] : list_of_values ;
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129       Patterns  statements  should be ordered with stict growing dates in the
130       series.
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133       The date may be either an absolute date or a relative date.   An  abso‐
134       lute  date is an integer followed by a time unit.  A relative date is a
135       '+' followed by an integer and a time unit (the reference is  the  date
136       of  the  previous  pattern description statement).  Legal time unit are
137       ps, ns, us and ms.
138              < 200 ps >,<4500ns>,< 12us > are legal absolute dates.   <  +200
139              ps >,<+4500ns>,<+1 us> are legal relative dates.
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142       A  label is an identifier (in VHDL syntax). The list_of_values is a set
143       of values. Each value is associated with one input-output. The value of
144       rank  i  corresponds to the i-th input-output. Depending on the format,
145       legal values for inputs are:
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148       B (binary)
149                 0 and, 1
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151       O (octal) 0, 1, 2, 3, 4, 5, 6 and, 7
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153       X (hexa.) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and, F
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156       For each output the user can predict a value. This bring the  simulator
157       to  make  a comparison between this value and the one calculated during
158       the simulation.  Predicting a ´*´ (star) as an  output  value  disables
159       the  comparison.  Values must be preceded by a ´?´ (question mark). The
160       ´?´ can be omitted when using a ´*´. Depending  on  the  format,  legal
161       values for outputs are :
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164       B (binary)
165                 0, 1 and *
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167       O (octal) 0, 1, 2, 3, 4, 5, 6, 7 and *
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169       X (hexa.) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F and *
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172       Using  the binary format ´?1´ can be replaced by ´+´ (plus) and ´?0´ by
173       ´-´ (minus).
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175
176       Example
177                 in  A (0 to 15) X;
178                 in  B (0 to 15) X;
179                 in  Cin;
180                 out Cout;
181                 signal S (0 to 15) X;
182                 register Accu.A (0 to 15) X;
183
184                 begin
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186                 <   0 ns > pattern_0 : F0F0 0A0A 1 ?0 ?FAFA ?6DE7;
187                 < +10 ns > pattern_1 : 0F0F F6F0 0  +  **** ?54FC;
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189                 end;
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191
192       Putting one or several additional ´;´ (semicolon) at the end of a  pat‐
193       tern  makes  one  or  several  blank lines (up to 15) be printed in the
194       result file after the pattern.
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197       Other statements (called actions) such as changing registers  value  or
198       saving the state of the circuit can be placed in the description block.
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201       The  content  of a register can be forced to a user defined value using
202       the following statement:
203              register_name <= value ;
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206       Register_name is a string representing the name of the register  to  be
207       forced (written in the same form as described above).
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210       Value can be given in hexadecimal (X), octal (O) or binary (B) format :
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212       Examples  X"0FE46"
213                 O"0345"
214                 B"01010111"
215                 "0111000"
216                 ´0´
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219       The  value of the register will be forced to value just before the pat‐
220       tern following the statement is executed.
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223       The state of the circuit can be saved after all patterns are  processed
224       using:
225              save;
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228       The  save;  statement  must be placed just before the end; instruction.
229       When writing a long sequence of patterns, this feature can be  used  to
230       split  the sequence into several small sequences (with a save statement
231       at the end of each sequence) (see asimut(1)).
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234       In pat format a comment begins with either a ´#´ (sharp) or a ´--´ (two
235       adjacent minus) and extends up to the end of the line. A comment marked
236       by a ´--´ is simply ignored. A comment maked by a ´#´ is kept  at  com‐
237       pile time and reproduced at the same place in the result file.
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DIAGNOSTICS

241       Pat does not make the difference between upper and lower case letters.
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244       When  the  specified  read-write  format  is  O  (octal)  for  an array
245       input-output and the range of the input-output doesn´t match a multiple
246       of  3,  the  most  significant  bits  -  1 or 2 bits - of the value are
247       ignored.
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250       When the specified read-write format is X (hexadecimal)  for  an  array
251       input-output and the range of the input-output doesn´t match a multiple
252       of 4, the most significant bits - 1, 2 or 3 bits -  of  the  value  are
253       ignored.
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256       A  comment beginning with a ´#´ (sharp) placed after the end; statement
257       causes a syntax error.
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SEE ALSO

261       asimut(1), genpat(1), libpat(3)
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268ASIM/LIP6                       October 1, 1997                         PAT(5)
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