1GBZ80(7)             BSD Miscellaneous Information Manual             GBZ80(7)
2

NAME

4     gbz80 — CPU opcode reference
5

DESCRIPTION

7     This is the list of opcodes supported by rgbasm(1), including a short
8     description, the number of bytes needed to encode them and the number of
9     CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete
10     them.
11
12     Note: All arithmetic/logic operations that use register A as destination
13     can omit the destination as it is assumed it's register A.  The following
14     two lines have the same effect:
15
16           OR A,B
17           OR B
18

LEGEND

20     List of abbreviations used in this document.
21
22     r8            Any of the 8-bit registers (A, B, C, D, E, H, L).
23
24     r16           Any of the general-purpose 16-bit registers (BC, DE, HL).
25
26     n8            8-bit integer constant.
27
28     n16           16-bit integer constant.
29
30     e8            8-bit offset (-128 to 127).
31
32     u3            3-bit unsigned integer constant (0 to 7).
33
34     cc            Condition codes:
35                   Z:      Execute if Z is set.
36                   NZ:     Execute if Z is not set.
37                   C:      Execute if C is set.
38                   NC:     Execute if C is not set.
39
40     vec           One of the RST vectors (0x00, 0x08, 0x10, 0x18, 0x20, 0x28,
41                   0x30 and 0x38).
42

INSTRUCTION OVERVIEW

44   8-bit Arithmetic and Logic Instructions
45     ADC A,r8
46     ADC A,[HL]
47     ADC A,n8
48     ADD A,r8
49     ADD A,[HL]
50     ADD A,n8
51     AND A,r8
52     AND A,[HL]
53     AND A,n8
54     CP A,r8
55     CP A,[HL]
56     CP A,n8
57     DEC r8
58     DEC [HL]
59     INC r8
60     INC [HL]
61     OR A,r8
62     OR A,[HL]
63     OR A,n8
64     SBC A,r8
65     SBC A,[HL]
66     SBC A,n8
67     SUB A,r8
68     SUB A,[HL]
69     SUB A,n8
70     XOR A,r8
71     XOR A,[HL]
72     XOR A,n8
73
74   16-bit Arithmetic Instructions
75     ADD HL,r16
76     DEC r16
77     INC r16
78
79   Bit Operations Instructions
80     BIT u3,r8
81     BIT u3,[HL]
82     RES u3,r8
83     RES u3,[HL]
84     SET u3,r8
85     SET u3,[HL]
86     SWAP r8
87     SWAP [HL]
88
89   Bit Shift Instructions
90     RL r8
91     RL [HL]
92     RLA
93     RLC r8
94     RLC [HL]
95     RLCA
96     RR r8
97     RR [HL]
98     RRA
99     RRC r8
100     RRC [HL]
101     RRCA
102     SLA r8
103     SLA [HL]
104     SRA r8
105     SRA [HL]
106     SRL r8
107     SRL [HL]
108
109   Load Instructions
110     LD r8,r8
111     LD r8,n8
112     LD r16,n16
113     LD [HL],r8
114     LD [HL],n8
115     LD r8,[HL]
116     LD [r16],A
117     LD [n16],A
118     LD [$FF00+n8],A
119     LD [$FF00+C],A
120     LD A,[r16]
121     LD A,[n16]
122     LD A,[$FF00+n8]
123     LD A,[$FF00+C]
124     LD [HL+],A
125     LD [HL-],A
126     LD A,[HL+]
127     LD A,[HL-]
128
129   Jumps and Subroutines
130     CALL n16
131     CALL cc,n16
132     JP HL
133     JP n16
134     JP cc,n16
135     JR e8
136     JR cc,e8
137     RET cc
138     RET
139     RETI
140     RST vec
141
142   Stack Operations Instructions
143     ADD HL,SP
144     ADD SP,e8
145     DEC SP
146     INC SP
147     LD SP,n16
148     LD [n16],SP
149     LD HL,SP+e8
150     LD SP,HL
151     POP AF
152     POP r16
153     PUSH AF
154     PUSH r16
155
156   Miscelaneous Instructions
157     CCF
158     CPL
159     DAA
160     DI
161     EI
162     HALT
163     NOP
164     SCF
165     STOP
166

INSTRUCTION REFERENCE

168   ADC A,r8
169     Add the value in r8 plus the carry flag to A.
170
171     Cycles: 1
172
173     Bytes: 1
174
175     Flags:
176     ·   Z: Set if result is 0.
177     ·   N: 0
178     ·   H: Set if overflow from bit 3.
179     ·   C: Set if overflow from bit 7.
180
181   ADC A,[HL]
182     Add the value pointed by HL plus the carry flag to A.
183
184     Cycles: 2
185
186     Bytes: 1
187
188     Flags: See ADC A,r8
189
190   ADC A,n8
191     Add the value n8 plus the carry flag to A.
192
193     Cycles: 2
194
195     Bytes: 2
196
197     Flags: See ADC A,r8
198
199   ADD A,r8
200     Add the value in r8 to A.
201
202     Cycles: 1
203
204     Bytes: 1
205
206     Flags:
207     ·   Z: Set if result is 0.
208     ·   N: 0
209     ·   H: Set if overflow from bit 3.
210     ·   C: Set if overflow from bit 7.
211
212   ADD A,[HL]
213     Add the value pointed by HL to A.
214
215     Cycles: 2
216
217     Bytes: 1
218
219     Flags: See ADD A,r8
220
221   ADD A,n8
222     Add the value n8 to A.
223
224     Cycles: 2
225
226     Bytes: 2
227
228     Flags: See ADD A,r8
229
230   ADD HL,r16
231     Add the value in r16 to HL.
232
233     Cycles: 2
234
235     Bytes: 1
236
237     Flags:
238     ·   N: 0
239     ·   H: Set if overflow from bit 11.
240     ·   C: Set if overflow from bit 15.
241
242   ADD HL,SP
243     Add the value in SP to HL.
244
245     Cycles: 2
246
247     Bytes: 1
248
249     Flags: See ADD HL,r16
250
251   ADD SP,e8
252     Add the signed value e8 to SP.
253
254     Cycles: 4
255
256     Bytes: 2
257
258     Flags:
259     ·   Z: 0
260     ·   N: 0
261     ·   H: Set if overflow from bit 3.
262     ·   C: Set if overflow from bit 7.
263
264   AND A,r8
265     Bitwise AND between the value in r8 and A.
266
267     Cycles: 1
268
269     Bytes: 1
270
271     Flags:
272     ·   Z: Set if result is 0.
273     ·   N: 0
274     ·   H: 1
275     ·   C: 0
276
277   AND A,[HL]
278     Bitwise AND between the value pointed by HL and A.
279
280     Cycles: 2
281
282     Bytes: 1
283
284     Flags: See AND A,r8
285
286   AND A,n8
287     Bitwise AND between the value in n8 and A.
288
289     Cycles: 2
290
291     Bytes: 2
292
293     Flags: See AND A,r8
294
295   BIT u3,r8
296     Test bit u3 in register r8, set the zero flag if bit not set.
297
298     Cycles: 2
299
300     Bytes: 2
301
302     Flags:
303     ·   Z: Set if the selected bit is 0.
304     ·   N: 0
305     ·   H: 1
306
307   BIT u3,[HL]
308     Test bit u3 in the byte pointed by HL, set the zero flag if bit not set.
309
310     Cycles: 3
311
312     Bytes: 2
313
314     Flags: See BIT u3,r8
315
316   CALL n16
317     Call address n16.
318
319     Cycles: 6
320
321     Bytes: 3
322
323     Flags: None affected.
324
325   CALL cc,n16
326     Call address n16 if condition cc is met.
327
328     Cycles: 6/3
329
330     Bytes: 3
331
332     Flags: None affected.
333
334   CCF
335     Complement Carry Flag.
336
337     Cycles: 1
338
339     Bytes: 1
340
341     Flags:
342     ·   N: 0
343     ·   H: 0
344     ·   C: Complemented.
345
346   CP A,r8
347     Subtract the value in r8 from A and set flags accordingly, but don't
348     store the result.
349
350     Cycles: 1
351
352     Bytes: 1
353
354     Flags:
355     ·   Z: Set if result is 0.
356     ·   N: 1
357     ·   H: Set if no borrow from bit 4.
358     ·   C: Set if no borrow (set if r8 > A).
359
360   CP A,[HL]
361     Subtract the value pointed by HL from A and set flags accordingly, but
362     don't store the result.
363
364     Cycles: 2
365
366     Bytes: 1
367
368     Flags: See CP A,r8
369
370   CP A,n8
371     Subtract the value n8 from A and set flags accordingly, but don't store
372     the result.
373
374     Cycles: 2
375
376     Bytes: 2
377
378     Flags: See CP A,r8
379
380   CPL
381     Complement accumulator (A = ~A).
382
383     Cycles: 1
384
385     Bytes: 1
386
387     Flags:
388     ·   N: 1
389     ·   H: 1
390
391   DAA
392     Decimal adjust register A to get a correct BCD representation after an
393     arithmetic instruction.
394
395     Cycles: 1
396
397     Bytes: 1
398
399     Flags:
400     ·   Z: Set if result is 0.
401     ·   H: 0
402     ·   C: Set or reset depending on the operation.
403
404   DEC r8
405     Decrement value in register r8 by 1.
406
407     Cycles: 1
408
409     Bytes: 1
410
411     Flags:
412     ·   Z: Set if result is 0.
413     ·   N: 1
414     ·   H: Set if no borrow from bit 4.
415
416   DEC [HL]
417     Decrement the value pointed by HL by 1.
418
419     Cycles: 3
420
421     Bytes: 1
422
423     Flags: See DEC r8
424
425   DEC r16
426     Decrement value in register r16 by 1.
427
428     Cycles: 2
429
430     Bytes: 1
431
432     Flags: None affected.
433
434   DEC SP
435     Decrement value in register SP by 1.
436
437     Cycles: 2
438
439     Bytes: 1
440
441     Flags: None affected.
442
443   DI
444     Disable Interrupts.
445
446     Cycles: 1
447
448     Bytes: 1
449
450     Flags: None affected.
451
452   EI
453     Enable Interrupts.
454
455     Cycles: 1
456
457     Bytes: 1
458
459     Flags: None affected.
460
461   HALT
462     Enter CPU low power mode.
463
464     Cycles: -
465
466     Bytes: 1
467
468     Flags: None affected.
469
470   INC r8
471     Increment value in register r8 by 1.
472
473     Cycles: 1
474
475     Bytes: 1
476
477     Flags:
478     ·   Z: Set if result is 0.
479     ·   N: 0
480     ·   H: Set if overflow from bit 3.
481
482   INC [HL]
483     Increment the value pointed by HL by 1.
484
485     Cycles: 3
486
487     Bytes: 1
488
489     Flags: See INC r8
490
491   INC r16
492     Increment value in register r16 by 1.
493
494     Cycles: 2
495
496     Bytes: 1
497
498     Flags: None affected.
499
500   INC SP
501     Increment value in register SP by 1.
502
503     Cycles: 2
504
505     Bytes: 1
506
507     Flags: None affected.
508
509   JP n16
510     Absolute jump to address n16.
511
512     Cycles: 4
513
514     Bytes: 3
515
516     Flags: None affected.
517
518   JP cc,n16
519     Absolute jump to address n16 if condition cc is met.
520
521     Cycles: 4/3
522
523     Bytes: 3
524
525     Flags: None affected.
526
527   JP HL
528     Jump to address in HL, that is, load PC with value in register HL.
529
530     Cycles: 1
531
532     Bytes: 1
533
534     Flags: None affected.
535
536   JR e8
537     Relative jump by adding e8 to the current address.
538
539     Cycles: 3
540
541     Bytes: 2
542
543     Flags: None affected.
544
545   JR cc,e8
546     Relative jump by adding e8 to the current address if condition cc is met.
547
548     Cycles: 3/2
549
550     Bytes: 2
551
552     Flags: None affected.
553
554   LD r8,r8
555     Store value in register on the right into register on the left.
556
557     Cycles: 1
558
559     Bytes: 1
560
561     Flags: None affected.
562
563   LD r8,n8
564     Load value n8 into register r8.
565
566     Cycles: 2
567
568     Bytes: 2
569
570     Flags: None affected.
571
572   LD r16,n16
573     Load value n16 into register r16.
574
575     Cycles: 3
576
577     Bytes: 3
578
579     Flags: None affected.
580
581   LD [HL],r8
582     Store value in register r8 into byte pointed by register HL.
583
584     Cycles: 2
585
586     Bytes: 1
587
588     Flags: None affected.
589
590   LD [HL],n8
591     Store value n8 into byte pointed by register HL.
592
593     Cycles: 3
594
595     Bytes: 2
596
597     Flags: None affected.
598
599   LD r8,[HL]
600     Load value into register r8 from byte pointed by register HL.
601
602     Cycles: 2
603
604     Bytes: 1
605
606     Flags: None affected.
607
608   LD [r16],A
609     Store value in register A into address pointed by register r16.
610
611     Cycles: 2
612
613     Bytes: 1
614
615     Flags: None affected.
616
617   LD [n16],A
618     Store value in register A into address n16.
619
620     Cycles: 4
621
622     Bytes: 3
623
624     Flags: None affected.
625
626   LD [$FF00+n8],A
627     Store value in register A into high RAM or I/O registers.
628
629     The following synonym forces this encoding: LDH [$FF00+n8],A
630
631     Cycles: 3
632
633     Bytes: 2
634
635     Flags: None affected.
636
637   LD [$FF00+C],A
638     Store value in register A into high RAM or I/O registers.
639
640     Cycles: 2
641
642     Bytes: 1
643
644     Flags: None affected.
645
646   LD A,[r16]
647     Load value in register A from address pointed by register r16.
648
649     Cycles: 2
650
651     Bytes: 1
652
653     Flags: None affected.
654
655   LD A,[n16]
656     Load value in register A from address n16.
657
658     Cycles: 4
659
660     Bytes: 3
661
662     Flags: None affected.
663
664   LD A,[$FF00+n8]
665     Load value in register A from high RAM or I/O registers.
666
667     The following synonym forces this encoding: LDH A,[$FF00+n8]
668
669     Cycles: 3
670
671     Bytes: 2
672
673     Flags: None affected.
674
675   LD A,[$FF00+C]
676     Load value in register A from high RAM or I/O registers.
677
678     Cycles: 2
679
680     Bytes: 1
681
682     Flags: None affected.
683
684   LD [HL+],A
685     Store value in register A into byte pointed by HL and post-increment HL.
686
687     Cycles: 2
688
689     Bytes: 1
690
691     Flags: None affected.
692
693   LD [HL-],A
694     Store value in register A into byte pointed by HL and post-decrement HL.
695
696     Cycles: 2
697
698     Bytes: 1
699
700     Flags: None affected.
701
702   LD A,[HL+]
703     Load value into register A from byte pointed by HL and post-increment HL.
704
705     Cycles: 2
706
707     Bytes: 1
708
709     Flags: None affected.
710
711   LD A,[HL-]
712     Load value into register A from byte pointed by HL and post-decrement HL.
713
714     Cycles: 2
715
716     Bytes: 1
717
718     Flags: None affected.
719
720   LD SP,n16
721     Load value n16 into register SP.
722
723     Cycles: 3
724
725     Bytes: 3
726
727     Flags: None affected.
728
729   LD [n16],SP
730     Store SP into addresses n16 (LSB) and n16 + 1 (MSB).
731
732     Cycles: 5
733
734     Bytes: 3
735
736     Flags: None affected.
737
738   LD HL,SP+e8
739     Add the signed value e8 to SP and store the result in HL.
740
741     Cycles: 3
742
743     Bytes: 2
744
745     Flags:
746     ·   Z: 0
747     ·   N: 0
748     ·   H: Set if overflow from bit 3.
749     ·   C: Set if overflow from bit 7.
750
751   LD SP,HL
752     Load register HL into register SP.
753
754     Cycles: 2
755
756     Bytes: 1
757
758     Flags: None affected.
759
760   NOP
761     No operation.
762
763     Cycles: 1
764
765     Bytes: 1
766
767     Flags: None affected.
768
769   OR A,r8
770     Bitwise OR between the value in r8 and A.
771
772     Cycles: 1
773
774     Bytes: 1
775
776     Flags:
777     ·   Z: Set if result is 0.
778     ·   N: 0
779     ·   H: 0
780     ·   C: 0
781
782   OR A,[HL]
783     Bitwise OR between the value pointed by HL and A.
784
785     Cycles: 2
786
787     Bytes: 1
788
789     Flags: See OR A,r8
790
791   OR A,n8
792     Bitwise OR between the value in n8 and A.
793
794     Cycles: 2
795
796     Bytes: 2
797
798     Flags: See OR A,r8
799
800   POP AF
801     Pop register AF from the stack.
802
803     Cycles: 3
804
805     Bytes: 1
806
807     Flags: None affected.
808
809   POP r16
810     Pop register r16 from the stack.
811
812     Cycles: 3
813
814     Bytes: 1
815
816     Flags: None affected.
817
818   PUSH AF
819     Push register AF into the stack.
820
821     Cycles: 4
822
823     Bytes: 1
824
825     Flags: None affected.
826
827   PUSH r16
828     Push register r16 into the stack.
829
830     Cycles: 4
831
832     Bytes: 1
833
834     Flags: None affected.
835
836   RES u3,r8
837     Set bit u3 in register r8 to 0.
838
839     Cycles: 2
840
841     Bytes: 2
842
843     Flags: None affected.
844
845   RES u3,[HL]
846     Set bit u3 in the byte pointed by HL to 0.
847
848     Cycles: 4
849
850     Bytes: 2
851
852     Flags: None affected.
853
854   RET
855     Return from subroutine.
856
857     Cycles: 4
858
859     Bytes: 1
860
861     Flags: None affected.
862
863   RET cc
864     Return from subroutine if condition cc is met.
865
866     Cycles: 5/2
867
868     Bytes: 1
869
870     Flags: None affected.
871
872   RETI
873     Return from subroutine and enable interrupts.
874
875     Cycles: 4
876
877     Bytes: 1
878
879     Flags: None affected.
880
881   RL r8
882     Rotate register r8 left through carry.
883
884           C <- [7 <- 0] <- C
885
886     Cycles: 2
887
888     Bytes: 2
889
890     Flags:
891     ·   Z: Set if result is 0.
892     ·   N: 0
893     ·   H: 0
894     ·   C: Set according to result.
895
896   RL [HL]
897     Rotate value pointed by HL left through carry.
898
899           C <- [7 <- 0] <- C
900
901     Cycles: 4
902
903     Bytes: 2
904
905     Flags: See RL r8
906
907   RLA
908     Rotate register A left through carry.
909
910           C <- [7 <- 0] <- C
911
912     Cycles: 1
913
914     Bytes: 1
915
916     Flags:
917     ·   Z: 0
918     ·   N: 0
919     ·   H: 0
920     ·   C: Set according to result.
921
922   RLC r8
923     Rotate register r8 left.
924
925           C <- [7 <- 0] <- [7]
926
927     Cycles: 2
928
929     Bytes: 2
930
931     Flags:
932     ·   Z: Set if result is 0.
933     ·   N: 0
934     ·   H: 0
935     ·   C: Set according to result.
936
937   RLC [HL]
938     Rotate value pointed by HL left.
939
940           C <- [7 <- 0] <- [7]
941
942     Cycles: 4
943
944     Bytes: 2
945
946     Flags: See RLC r8
947
948   RLCA
949     Rotate register A left.
950
951           C <- [7 <- 0] <- [7]
952
953     Cycles: 1
954
955     Bytes: 1
956
957     Flags:
958     ·   Z: 0
959     ·   N: 0
960     ·   H: 0
961     ·   C: Set according to result.
962
963   RR r8
964     Rotate register r8 right through carry.
965
966           C -> [7 -> 0] -> C
967
968     Cycles: 2
969
970     Bytes: 2
971
972     Flags:
973     ·   Z: Set if result is 0.
974     ·   N: 0
975     ·   H: 0
976     ·   C: Set according to result.
977
978   RR [HL]
979     Rotate value pointed by HL right through carry.
980
981           C -> [7 -> 0] -> C
982
983     Cycles: 4
984
985     Bytes: 2
986
987     Flags: See RR r8
988
989   RRA
990     Rotate register A right through carry.
991
992           C -> [7 -> 0] -> C
993
994     Cycles: 1
995
996     Bytes: 1
997
998     Flags:
999     ·   Z: 0
1000     ·   N: 0
1001     ·   H: 0
1002     ·   C: Set according to result.
1003
1004   RRC r8
1005     Rotate register r8 right.
1006
1007           [0] -> [7 -> 0] -> C
1008
1009     Cycles: 2
1010
1011     Bytes: 2
1012
1013     Flags:
1014     ·   Z: Set if result is 0.
1015     ·   N: 0
1016     ·   H: 0
1017     ·   C: Set according to result.
1018
1019   RRC [HL]
1020     Rotate value pointed by HL right.
1021
1022           [0] -> [7 -> 0] -> C
1023
1024     Cycles: 4
1025
1026     Bytes: 2
1027
1028     Flags: See RRC r8
1029
1030   RRCA
1031     Rotate register A right.
1032
1033           [0] -> [7 -> 0] -> C
1034
1035     Cycles: 1
1036
1037     Bytes: 1
1038
1039     Flags:
1040     ·   Z: 0
1041     ·   N: 0
1042     ·   H: 0
1043     ·   C: Set according to result.
1044
1045   RST vec
1046     Call restart vector vec.
1047
1048     Cycles: 4
1049
1050     Bytes: 1
1051
1052     Flags: None affected.
1053
1054   SBC A,r8
1055     Subtract the value in r8 and the carry flag from A.
1056
1057     Cycles: 1
1058
1059     Bytes: 1
1060
1061     Flags:
1062     ·   Z: Set if result is 0.
1063     ·   N: 1
1064     ·   H: Set if no borrow from bit 4.
1065     ·   C: Set if no borrow (set if r8 > A).
1066
1067   SBC A,[HL]
1068     Subtract the value pointed by HL and the carry flag from A.
1069
1070     Cycles: 2
1071
1072     Bytes: 1
1073
1074     Flags: See SBC A,r8
1075
1076   SBC A,n8
1077     Subtract the value n8 and the carry flag from A.
1078
1079     Cycles: 2
1080
1081     Bytes: 2
1082
1083     Flags: See SBC A,r8
1084
1085   SCF
1086     Set Carry Flag.
1087
1088     Cycles: 1
1089
1090     Bytes: 1
1091
1092     Flags:
1093     ·   N: 0
1094     ·   H: 0
1095     ·   C: 1
1096
1097   SET u3,r8
1098     Set bit u3 in register r8 to 1.
1099
1100     Cycles: 2
1101
1102     Bytes: 2
1103
1104     Flags: None affected.
1105
1106   SET u3,[HL]
1107     Set bit u3 in the byte pointed by HL to 1.
1108
1109     Cycles: 4
1110
1111     Bytes: 2
1112
1113     Flags: None affected.
1114
1115   SLA r8
1116     Shift left arithmetic register r8.
1117
1118           C <- [7 <- 0] <- 0
1119
1120     Cycles: 2
1121
1122     Bytes: 2
1123
1124     Flags:
1125     ·   Z: Set if result is 0.
1126     ·   N: 0
1127     ·   H: 0
1128     ·   C: Set according to result.
1129
1130   SLA [HL]
1131     Shift left arithmetic value pointed by HL.
1132
1133           C <- [7 <- 0] <- 0
1134
1135     Cycles: 4
1136
1137     Bytes: 2
1138
1139     Flags: See SLA r8
1140
1141   SRA r8
1142     Shift right arithmetic register r8.
1143
1144           [7] -> [7 -> 0] -> C
1145
1146     Cycles: 2
1147
1148     Bytes: 2
1149
1150     Flags:
1151     ·   Z: Set if result is 0.
1152     ·   N: 0
1153     ·   H: 0
1154     ·   C: Set according to result.
1155
1156   SRA [HL]
1157     Shift right arithmetic value pointed by HL.
1158
1159           [7] -> [7 -> 0] -> C
1160
1161     Cycles: 4
1162
1163     Bytes: 2
1164
1165     Flags: See SRA r8
1166
1167   SRL r8
1168     Shift right logic register r8.
1169
1170           0 -> [7 -> 0] -> C
1171
1172     Cycles: 2
1173
1174     Bytes: 2
1175
1176     Flags:
1177     ·   Z: Set if result is 0.
1178     ·   N: 0
1179     ·   H: 0
1180     ·   C: Set according to result.
1181
1182   SRL [HL]
1183     Shift right logic value pointed by HL.
1184
1185           0 -> [7 -> 0] -> C
1186
1187     Cycles: 4
1188
1189     Bytes: 2
1190
1191     Flags: See SRA r8
1192
1193   STOP
1194     Enter CPU very low power mode.  Also used to switch between doube speed
1195     and normal CPU modes in GBC.
1196
1197     Cycles: -
1198
1199     Bytes: 2
1200
1201     Flags: None affected.
1202
1203   SUB A,r8
1204     Subtract the value in r8 from A.
1205
1206     Cycles: 1
1207
1208     Bytes: 1
1209
1210     Flags:
1211     ·   Z: Set if result is 0.
1212     ·   N: 1
1213     ·   H: Set if no borrow from bit 4.
1214     ·   C: Set if no borrow (set if r8 > A).
1215
1216   SUB A,[HL]
1217     Subtract the value pointed by HL from A.
1218
1219     Cycles: 2
1220
1221     Bytes: 1
1222
1223     Flags: See SUB A,r8
1224
1225   SUB A,n8
1226     Subtract the value n8 from A.
1227
1228     Cycles: 2
1229
1230     Bytes: 2
1231
1232     Flags: See SUB A,r8
1233
1234   SWAP r8
1235     Swap upper 4 bits in register r8 and the lower ones.
1236
1237     Cycles: 2
1238
1239     Bytes: 2
1240
1241     Flags:
1242     ·   Z: Set if result is 0.
1243     ·   N: 0
1244     ·   H: 0
1245     ·   C: 0
1246
1247   SWAP [HL]
1248     Swap upper 4 bits in the byte pointed by HL and the lower ones.
1249
1250     Cycles: 4
1251
1252     Bytes: 2
1253
1254     Flags: See SWAP r8
1255
1256   XOR A,r8
1257     Bitwise XOR between the value in r8 and A.
1258
1259     Cycles: 1
1260
1261     Bytes: 1
1262
1263     Flags:
1264     ·   Z: Set if result is 0.
1265     ·   N: 0
1266     ·   H: 0
1267     ·   C: 0
1268
1269   XOR A,[HL]
1270     Bitwise XOR between the value pointed by HL and A.
1271
1272     Cycles: 2
1273
1274     Bytes: 1
1275
1276     Flags: See XOR A,r8
1277
1278   XOR A,n8
1279     Bitwise XOR between the value in n8 and A.
1280
1281     Cycles: 2
1282
1283     Bytes: 2
1284
1285     Flags: See XOR A,r8
1286

SEE ALSO

1288     rgbasm(1), rgbds(7)
1289

HISTORY

1291     rgbds was originally written by Carsten Sørensen as part of the ASMotor
1292     package, and was later packaged in RGBDS by Justin Lloyd.  It is now
1293     maintained by a number of contributors at .:
1294           https://github.com/rednex/rgbds
1295
1296RGBDS Manual                    April 17, 2017                    RGBDS Manual
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