1electric(1)                 General Commands Manual                electric(1)
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NAME

6       electric - a VLSI design system
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SYNOPSIS

10       electric [-m] [-t technology] [library]
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DESCRIPTION

14       Electric  is  a  general  purpose system for all electrical design.  It
15       currently  knows  about  nMOS,  CMOS,  Bipolar,  artwork,   schematics,
16       printed-circuit  boards,  and many other technologies.  Its has a large
17       set of tools including multiple design-rule checkers (both  incremental
18       and  hierarchical), an electrical rules checker, over a dozen simulator
19       interfaces, multiple generators (PLA and pad frame),  multiple  routers
20       (stitching, maze, river), network comparison, compaction, compensation,
21       a VHDL compiler, and a silicon compiler that places-and-routes standard
22       cells.
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24       In  addition  to the text terminal used to invoke the program, Electric
25       uses a color display with a mouse as a work station.  Separate  windows
26       are used for text and graphics.
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28       If  a  library disk file is mentioned on the command line, that file is
29       read as the initial design for editing.   In  addition,  the  following
30       switches are recognized:
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32       -t     specifies  an  initial technology.  The argument must be a tech‐
33              nology name such as "nmos", "cmos", "mocmos" (MOSIS CMOS), "moc‐
34              mossub"  (MOSIS  CMOS  Submicron),  "bipolar"  (simple Bipolar),
35              "schematic" (Schematic capture), or "artwork" (sketchpad mode).
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37       -m     specifies there may  be  multiple  monitors  and  that  Electric
38              should look for them.
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REPRESENTATION

42       Circuits  are represented as networks that contain nodes and connecting
43       arcs.  The nodes are electrical components such as  transistors,  logic
44       gates, and contacts.  The arcs are simply wires that connect the nodes.
45       In addition, each node has a set of ports which are the  sites  of  arc
46       connection.  A technology, then, is simply a set of primitive nodes and
47       arcs that are the building blocks of circuits designed in that environ‐
48       ment.
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50       Collections  of  nodes  and  arcs can also be aggregated into facets of
51       cells which can be used higher in the hierarchy to act as nodes.  These
52       user-defined nodes have ports that come from internal nodes whose ports
53       are exported.  Facets are collected in libraries which contain a  hier‐
54       archically consistent design.
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56       Arcs  have  properties that help constrain the design.  For example, an
57       arc may rotate arbitrarily or be fixed in their angle.  Arcs  can  also
58       be  stretchable  or rigid under modification of their connecting nodes.
59       These constraints propagate hierarchically from the bottom-up.
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TECHNOLOGIES

63       A large set of technologies is provided in Electric.  These can be mod‐
64       ified with the technology editor, or completely new technologies can be
65       created.  The following paragraphs describe some of the basic technolo‐
66       gies.
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68       The  nMOS  technologies  have arcs available in Metal, Polysilicon, and
69       Diffusion.  The primitive nodes include normal  contacts,  buried  con‐
70       tacts, transistors, and "pins" for making arc corners.  Transistors may
71       be serpentine and the pure layer nodes  may  be  polygonally  described
72       with  the  node  trace command.  The "nmos" technology has the standard
73       Mead&Conway design rules.
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75       The CMOS technologies have arcs available in  Metal,  Polysilicon,  and
76       Diffusion.  The Diffusion arcs may be found in a P-well implant or in a
77       P implant.  Thus, there are two types of  metal-to-diffusion  contacts,
78       two  types  of  diffusion pins, and two types of transistors: in P-well
79       and in P implant.  As with nMOS, the transistors may be serpentine  and
80       the pure layer primitives may be polygonally defined.  The "cmos" tech‐
81       nology has the standard design rules according to Griswold;  the  "moc‐
82       mos"  technology  has  design  rules for the MOSIS CMOS process (double
83       metal); the "mocmossub" technology has design rules for the MOSIS  CMOS
84       Submicron process (double poly and up to 6 metal); the "rcmos" technol‐
85       ogy has round geometry for the MOSIS CMOS process.
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87       The "schematic" technology provides basic symbols for  doing  schematic
88       capture.   It  contains  the  logic  symbols: BUFFER, AND, OR, and XOR.
89       Negating bubbles can be placed by negating a connecting arc.  There are
90       also  more  complex  components  such as flip-flop, off-page-connector,
91       black-box, meter, and power source.  Finally, there are the  electrical
92       components:  transistor, resistor, diode, capacitor, and inductor.  Two
93       arc types exist for normal wires and variable-width busses.
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95       The "artwork" technology is a sketchpad environment for doing  general-
96       purpose  graphics.   Components  can be placed with arbitrary color and
97       shape.
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99       The "generic" technology exists for those miscellaneous  purposes  that
100       do  not fall into the domain of other technologies.  It has the univer‐
101       sal arc and pin which can connect to ANY other object and are therefore
102       useful  in mixed-technology designs.  The invisible arc can be used for
103       constraining two nodes without making a connection.  The  unrouted  arc
104       can be used for electrical connections that are to be routed later with
105       real wires.  The  facet-center  primitive,  when  placed  in  a  facet,
106       defines the cursor origin on instances of that facet.
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108

DESIGN-RULE CHECKING

110       The  incremental  design-rule  checker  is  normally on and watches all
111       changes made to the circuit.  It does not correct but prints error mes‐
112       sages when design rules are violated.  Hierarchy is not handled, so the
113       contents of subfacets are not checked.
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115       The hierarchical checker looks all the way down  the  circuit  for  all
116       design-rules.   Another  option  allows  an  input deck to prepared for
117       ECAD's Dracula design-rule checker.
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COMPACTION

121       The compactor attempts to reduce the size of a facet by removing unnec‐
122       essary  space  between  elements.   When invoked it will compact in the
123       vertical and horizontal directions until it can find no way to  compact
124       the  facet  any  further.  It does not do hierarchical compaction, does
125       not guarantee optimal compaction, nor can it handle non-manhattan geom‐
126       etry properly.  The compactor will also spread out the facet to guaran‐
127       tee no design-rule violations, if the "spread" option is set.
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SIMULATION

131       There are many  simulator  interfaces:  ESIM  (the  default  simulator:
132       switch-level  for nMOS without timing), RSIM (switch-level for MOS with
133       timing), RNL (switch-level for MOS with  timing  and  LISP  front-end),
134       MOSSIM (switch-level for MOS with timing), COSMOS (switch-level for MOS
135       with timing), VERILOG (Cadence simulator), TEXSIM (a commercial simula‐
136       tor), SILOS (a commercial simulator), ABEL (PAL generator/simulator for
137       schematic),  and  SPICE  (circuit  level).   MOSSIM,  COSMOS,  VERILOG,
138       TEXSIM,  SILOS,  and  ABEL do not actually simulate: they only write an
139       input deck of your circuit.
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141       In preparation for most simulators, it is  necessary  to  export  those
142       ports  that  you  wish  to manipulate or examine.  You must also export
143       power and ground ports.
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145       In preparation for SPICE simulation, you must export power  and  ground
146       signals  and.   explicitly  connect  them  to source nodes.  The source
147       should then be parameterized to indicate the amount and whether  it  is
148       voltage  or  current.   For  example, to make a 5 volt supply, create a
149       source node and set the SPICE card to: "DC 5".  Next, all  input  ports
150       must  be exported and connected to the positive side of sources.  Next,
151       all values that are being plotted must be exported and have meter nodes
152       placed  on  them.   The  node should have the top and bottom ports con‐
153       nected appropriately.
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155

PLA GENERATION

157       There are two PLA generators, one specific to nMOS layout, and  another
158       specific to CMOS layout.  The nMOS PLA generator reads a single person‐
159       ality table and generates the array and all driving circuitry including
160       power and ground connections.  The CMOS PLA generator reads two person‐
161       ality tables (AND and OR) and also reads a library of PLA helper compo‐
162       nents (called "pla_mocmos") and generates the array.
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ROUTING

166       The  router is able to do river routing, maze routing, and simple facet
167       stitching (the explicit  wiring  of  implicitly  connected  nodes  that
168       abut).   River  routing  runs  a  bus of wires between the two opposite
169       sides of a routing channel.  The connections on each side must be in  a
170       line  so  that  the  bus runs between two parallel sets of points.  You
171       must use the Unrouted arc from the Generic technology to  indicate  the
172       ports  to be connected.  The river router can also connect wires to the
173       perpendicular sides of the routing channel  if  one  or  more  Unrouted
174       wires cross these sides.
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176       There  are two stitching modes: auto stitching and mimic stitching.  In
177       auto stitching, all ports  that  physically  touch  will  be  stitched.
178       Mimic stitching watches arcs that are created by the user and adds sim‐
179       ilar ones at other places in the facet.
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181

NETWORK COMPARISON

183       The network maintainer tool is able to compare the networks in the  two
184       facets  being  displayed  on  the  screen.  Once compared, nodes in one
185       facet can be equated with nodes in the other.  If the two networks  are
186       automorphic or otherwise difficult to distinguish, equivalence informa‐
187       tion can be specified prior to comparison by selecting a  component  in
188       the first facet then selecting a component in the second facet.
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AUTHOR

192       Steven M. Rubin
193          Static Free Software
194          4119 Alpine Road
195          Portola Valley, Ca 94028
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197       Also a cast of thousands:
198          Philip Attfield (Queens University): Polygon merging, facet dates
199          Ron Bolton (University of Saskatchewan): Miscellaneous help
200          Mark Brinsmead (Calgary): Apollo porting
201          Stefano Concina (Schlumberger): Polygon clipping
202          Peter Gallant (Queen's University): ALS simulation
203          T. J. Goodman (University of Canterbury) TEXSIM simulation
204          D. Guptill (Technical University of Nova Scotia): X-window interface
205          Robert Hon (Columbia University): CIF input
206          Sundaravarathan Iyengar (Case Western Reserve University): nMOS PLA generator
207          Allan Jost (Technical University of Nova Scotia): X-window interface
208          Wallace Kroeker (University of Calgary): Digital filter technology, CMOS PLA generator
209          Andrew Kostiuk (Queen's University): QUISC 1.0 Silicon compiler
210          Glen Lawson (S-MOS Systems): GDS-II input
211          David Lewis (University of Toronto): Short circuit checker
212          John Mohammed (Schlumberger): Miscellaneous help
213          Mark Moraes (University of Toronto): X-window interface
214          Sid Penstone (Queens University): many technologies, GDS-II output, SPICE improvements, SILOS simulation, GENERIC simulation
215          J. P. Polonovski (Ecole Polytechnique, France): Memory management improvement
216          Kevin Ryan (Technical University of Nova Scotia): X-window interface
217          Nora Ryan (Schlumberger): Technology translation, Compaction
218          Brent Serbin (Queen's University): ALS Simulator
219          Lyndon Swab (Queen's University): Northern Telecom CMOS technologies
220          Brian W. Thomson (University of Toronto): Mimic stitcher, RSIM interface
221          Burnie West (Schlumberger): Network maintainer help, bipolar technology
222          Telle Whitney (Schlumberger): River router
223          Rob Winstanley (University of Calgary): CIF input, RNL interface
224          Russell Wright (Queen's University): Lots of help
225          David J. Yurach (Queen's University): QUISC 2.0 Silicon compiler
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SEE ALSO

229       Rubin,  Steven  M.,  "A  General-Purpose Framework for CAD Algorithms",
230       IEEE Communications, Special Issue  on  Communications  and  VLSI,  May
231       1991.
232       Rubin,  Steven M., Computer Aids for VLSI Design, Addison-Wesley, Read‐
233       ing, Massachusetts, 1987.
234       Rubin, Steven M., "An Integrated Aid for Top-Down  Electrical  Design",
235       Proceedings, VLSI '83 (Anceau and Aas, eds.), North Holland, Amsterdam,
236       1983.
237       Mead, C. and Conway, L., Introduction to VLSI Systems,  Addison-Wesley,
238       1980.
239       Electrical User's Guide.
240       Electric Internals manual.
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FILES

244       ~/.cadrc         Personal startup file
245       ~/electric.log   Session logging file
246       *.elib           Binary input/output files
247       *.txt            Text input/output files
248       *.cif            CIF input/output files
249       *.pla            PLA personality input files
250       *.map            Color map files
251       *.mac            Macro files
252       *.sim            ESIM, RSIM, RNL, and COSMOS simulation output
253       rsim.in          RSIM simulation binary output
254       rnl.in           RNL simulation binary output
255       *.spi            SPICE simulation output
256       *.ver            VERILOG simulation output
257       *.ntk            MOSSIM simulation output
258       *.sil            SILOS simulation output
259       *.tdl            TEXSIM simulation output
260       *.pal            ABLE PAL simulation output
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265                                   11/12/00                        electric(1)
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