1SXLIB(5)                   CAO-VLSI Reference Manual                  SXLIB(5)
2
3
4

NAME

6       sxlib - a portable CMOS Standard Cell Library
7
8

DESCRIPTION

10       sxlib library contains standard cells that have been developed at UPMC-
11       ASIM/LIP6. This manual gives the list of available  cells,  with  their
12       behavior, width, maximum delay and input fan-in. This manual gives also
13       few thumb rules to help the user to well use the cells. The given delay
14       are  the  maximum  (that  means  worst  case  for  a generic .35 micron
15       process).  More precise delay can be found in  ALLIANCE  VHDL  behavior
16       files  (.vbe  file).   Cell-name  is  built that way <behavior>_<output
17       drive> (see explanations below).
18
19       Four files are attached to each cell:-
20       - ALLIANCE Layout ............... cell-name.ap
21       - ALLIANCE Transistor net-list .. cell-name.al
22       - ALLIANCE VHDL behavior ........ cell-name.vbe
23       - Compiled HILO behavior ........ 0000000xx.dat
24
25       And few files more:-
26       - CATAL ......................... ALLIANCE catalog file
27       - sxlib.cct ..................... Cell definition for HILO CAD tools
28       - CIRCUIT.idx ................... HILO catalog file
29       - sxlib.lib ..................... Cell definition for Synopsys CAD tools
30       - sxlib.db ...................... Compiled cell definition for Synopsys
31       - sxlib.sdb ..................... Icon definition for Synopys
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33
34

PHYSICAL OUTLINE

36       sxlib uses the symbolic layout promoted by Alliance in order to provide
37       process  independence.  All dimensions are in lambda units. The mapping
38       to a specific process CIF or GDS2 layout must be performed by  the  s2r
39       tool  (symbolic  to  real),  which  uses a value for the lambda (e.g. 1
40       lambda=0.3um).
41
42              _________________
43          50 |       VDD       |
44          45 |_________________|     x : place of virtual connector.
45          40 |           x     |
46          35 |        x  x     |         they are named : name_<y>
47          30 |  x     x        |
48          25 |  x     x        |         for example : i0_20
49          20 |  x              |                       i0_25
50          15 |           x     |                       i0_30
51          10 |_________________|
52           5 |       VSS       |
53           0 |_________________|
54             0  5 10 15 20 25 30
55
56       All cells are 50 lambdas high and N times 5 lambdas wide,  where  N  is
57       the  number  of pitches. That is the only physical information given in
58       the cell list below.  Power supplies are in horizontal ALU1 and  are  6
59       lambdas  wide.   Connectors are inside the cells, placed on a 5x5 grid.
60       Half layout design rules are a warranty for  any  layer  on  any  face,
61       except  for  the  power  supply and NWELL.  Cells can be abutted in all
62       directions whenever the supply is well  connected  and  connectors  are
63       always placed on the 5x5 grid.
64
65

DELAY MODEL

67       Cells  have  been  extracted  and  simulated  by using a generic 0.35um
68       process in order to give realistic values for the  delays  and  capaci‐
69       tances.   We chose to give only the worst delay for each output signal,
70       though it is not very realistic (since delay depends on each input,  an
71       input  can be easily up to twice faster than another). However, we just
72       wanted to give an idea of the relative delay.
73
74       Furthermore, we added 0.6ns to each output delay in order to take  into
75       account  the  delay due to the signal commutation. We have supposed the
76       output drives the maximum capacitance. This capacitance have been  com‐
77       puted  as  follow.  We  considered  that  a  good slope signal for this
78       process was 0.8ns.  Then we searched for the  capacitance  required  to
79       obtain the same input and output slope (0.8ns) for the smaller inverter
80       (inv_x1). That was 125fF. We simulated the same inverter without output
81       capacitance.  The  delay difference was about 0.6ns. This result is not
82       exactly the same for all cells, but 0.6ns is a good approximation.
83
84       The given delay is then a worst case (70degree, 2.7Volt, slow  process,
85       worst  input),  an  idea of the typical delay can be obtain by dividing
86       worst delay by 1.5, and best delay by dividing  by  2.   More  detailed
87       data  can  be  found in GENERIC data included in the VHDL files (.vbe).
88       Examples can be found at the end of this manual.
89
90       At last, to get a very better idea about the real delay  without  simu‐
91       lating  the spice transistor netlist, it is required to use the TAS (1)
92       tool, which is a timing static analyzer able to give the longer and the
93       shorter path for a given process.
94
95

OUTPUT DRIVE

97       The  output drive of a cell gives an information on the faculty for the
98       cell to drive a big capacitance. This faculty depends on the rising and
99       falling  output  resistance. The smaller the resistance, the bigger can
100       be the capacitance.  Minimum drive  is  x1.  This  corresponds  to  the
101       smallest  available  inverter (inv_x1). x2 means the cell is equivalent
102       (from the driving point of view) at two smaller inverters in  parallel,
103       and so on.
104
105       The  maximum  output  drive is x8. It is limited because of the maximum
106       output slope and the maximum authorized instantaneous  current.  If  it
107       was  bigger  the  output  slope could be very tight and the current too
108       big.
109
110       With the 0.35um process, an x1 is able to  drive  about  125fF,  x2  ->
111       250fF, x4 -> 500fF,x8 -> 1000fF.  This is just an indication since if a
112       cell is overloaded, the only consequence is to increase the propagation
113       time.  On  the  other  hand,  it  is not very good to under-load a cell
114       because this leads to a signal overshoot.  Actually, for big gate, such
115       as  noa3ao322_x1,  x1  means  maximal driving strength reachable with a
116       single logic layer, that can be much less than an inv_x1. That  is  why
117       is  the cell list below contains more precise drive strengh. As you can
118       see noa3ao322_x1 as a output drive strengh of 0.6, that means 0.6  time
119       an inverter, so say it can drive about 0.6*125fF=75fF.
120
121       With  the 0.35um process, a 1 lambda interconnect wire is about 0.15fF,
122       an average cell fan-in is 10fF. Then, if it needs about 50  lambdas  to
123       connect   2  cells,  an  x1  cell  is  able  to  drive  about  7  cells
124       (125/(10+50*.15)=7). With 100 lambdas, 5 cells, with 750 lambdas only 2
125       cells.  Note  that  50 lambdas means cells are very close one from each
126       other, nearly abutted, 100 lambdas is an average value.
127
128       All this are indications.  Only a  timing  analysis  on  the  extracted
129       transistor  net-list from layout can tell if a cell is well used or not
130       (see tas(1) for informations about static timing analysis).
131
132

BEHAVIOR

134       For most of cells, the user can deduce the cell behavior just by  read‐
135       ing its name.  That is very intuitive for inverter and more complex for
136       and/or cells.  For the last, the name gives the and/or tree  structure.
137       The  input  order for the VHDL interface component is always the alpha‐
138       betic order.
139
140       inv           : inversor buffer
141       buf           : buffer
142       [n]ts         : [not] tree-state
143       [n]xr<i>      : [not] xor <i> inputs
144       [n]mx<i>      : [not] multiplexor <i> inputs with coded command
145       [n][sd]ff<i>  : [not] [static|dynamic] flip-flop <i> inputs
146       [n]oa...      : [not] and/or function (see below)
147
148       and_or cell (YACC (1) grammar):-
149
150       NAME     : n OA_CELL                 -> not OA_CELL
151                | OA_CELL                   -> OA_CELL
152
153       OA_CELL  : OPERATOR INPUTS           -> function with INPUTS inputs
154                | OPERATOR OA_CELLS INPUTS  -> function with INPUTS inputs
155                                               where some inputs are OA_CELL
156
157       OPERATOR : a                         -> and
158                | o                         -> or
159                | n                         -> not
160
161       OA_CELLS : OA_CELLS OA_CELL          -> list of OA_CELL
162                | OA_CELL                   -> last OA_CELL of the list
163
164       INPUTS   : integer                   -> number of inputs
165
166       The input names are implicit and formed that way i<number>.
167       They are attributed in order beginning by i0.
168
169       nx where x is a number means there are x inverters in parallel. For
170       example an23 is an and with 3 inputs of which two are inverted, that
171       is and( not(i0), not(i1), i2).
172
173       Examples:- (some are not in sxlib)
174
175       na2       : not( and(i0,i1))
176       on12      : or( not(i0), i1)
177       noa2a22   : not( or( and(i0,i1), and(i2,i3)))
178       noa23     : not( or( and(i0,i1), i3))
179       noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7))
180
181       Note that xr2 could not be expressed with an and/or formulea even if
182       xr2 = or( and( not(i0), i1), and( not(i1), i0)) = oan12an122
183       but the input names are not well distributed.
184
185

CELL LIST

187       All available cells are listed below. The first  column  is  the  pitch
188       width.   The  pitch  value is 5 lambdas. The height is 50. Area is then
189       <number>*5*50.
190
191       The second column is the output drive strenght compared with the inv_x1
192       output drive strenght (see explanation above in section OUTPUT DRIVE).
193
194       The following column is the delay in nano-seconds.  Remember this delay
195       corresponds to the slower input+0.6ns (see explanation above in section
196       DELAY MODEL).
197
198       The  last column gives the function behavior with input capacitance.  /
199       means not, + means or, .  means and, ^ means xor.  Each input  is  fol‐
200       lowed  by  fan-in  capacitance in fF, (e.g. i0<11> means i0 pin capaci‐
201       tance is 11fF).
202
203       For some cells, such as fulladder, it was not  possible  to  internally
204       connect  all  inputs.  That means there are several inputs that must be
205       externally connected.  In the following list, these inputs are followed
206       by a star (*) character in the equation.
207
208       For  example,  fulladder  equation  is  sout  <=  (a* . b* . cin*).  a*
209       replaces a0, a1, a2, a3 that must be explicitly connected by the  user.
210       Note  also  few cells have more than one output. In that case there are
211       several lines in the list, one by output.
212       =================================================================
213       WIDTH NAME  DRIVE DELAY BEHAVIOR with cin
214       -------------------------------------------------------- INVERSOR
215        3 inv_x1       1.0 0.7  nq <= /i<8>
216        3 inv_x2       1.6 0.7  nq <= /i<12>
217        4 inv_x4       3.6 0.7  nq <= /i<26>
218        7 inv_x8       8.4 0.7  nq <= /i<54>
219       ---------------------------------------------------------- BUFFER
220        4 buf_x2       2.1 1.0   q <=  i<6>
221        5 buf_x4       4.3 1.0   q <=  i<9>
222        8 buf_x8       8.4 1.0   q <=  i<15>
223       ------------------------------------------------------ THREE STATE
224        6 nts_x1       1.2 0.8  IF (cmd<14>) nq <= /i<14>
225        8 nts_x2       2.4 0.9  IF (cmd<18>) nq <= /i<28>
226       10 ts_x4        4.3 1.1  IF (cmd<19>)  q <= i<8>
227       13 ts_x8        8.4 1.2  IF (cmd<19>)  q <= i<8>
228       -------------------------------------------------------------- AND
229        4 na2_x1       1.0 0.9  nq <= /(i0<11>.i1<11>)
230        7 na2_x4       4.3 1.2  nq <= /(i0<10>.i1<10>)
231        5 na3_x1       0.9 1.0  nq <= /(i0<11>.i1<11>.i2<11>)
232        8 na3_x4       4.3 1.3  nq <= /(i0<10>.i1<10>.i2<10>)
233        6 na4_x1       0.7 1.0  nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
234       10 na4_x4       4.3 1.4  nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
235        5 a2_x2        2.1 1.0   q <=  (i0<9>.i1<11>)
236        6 a2_x4        4.3 1.1   q <=  (i0<9>.i1<11>)
237        6 a3_x2        2.1 1.1   q <=  (i0<10>.i1<10>.i2<10>)
238        7 a3_x4        4.3 1.2   q <=  (i0<10>.i1<10>.i2<10>)
239        7 a4_x2        2.1 1.2   q <=  (i0<10>.i1<10>.i2<10>.i3<10>)
240        8 a4_x4        4.3 1.3   q <=  (i0<10>.i1<10>.i2<10>.i3<10>)
241        5 an12_x1      1.0 1.0   q <=  (/i0<12>).i1<9>
242        8 an12_x4      4.3 1.1   q <=  (/i0<9>).i1<11>
243       --------------------------------------------------------------- OR
244        4 no2_x1       1.0 0.9  nq <= /(i0<12>+i1<12>)
245        8 no2_x4       4.3 1.2  nq <= /(i0<12>+i1<11>)
246        5 no3_x1       0.8 1.0  nq <= /(i0<12>+i1<12>+i2<12>)
247        8 no3_x4       4.3 1.3  nq <= /(i0<12>+i1<12>+i2<11>)
248        6 no4_x1       0.6 1.1  nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
249       10 no4_x4       4.3 1.4  nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
250        5 o2_x2        2.1 1.0   q <=  (i0<10>+i1<10>)
251        6 o2_x4        4.3 1.1   q <=  (i0<10>+i1<10>)
252        6 o3_x2        2.1 1.1   q <=  (i0<10>+i1<10>+i2<9>)
253       10 o3_x4        4.3 1.2   q <=  (i0<10>+i1<10>+i2<9>)
254        7 o4_x2        2.1 1.2   q <=  (i0<10>+i1<10>+i2<10>+i3<9>)
255        8 o4_x4        4.3 1.3   q <=  (i0<12>+i1<12>+i2<12>+i3<12>)
256        5 on12_x1      1.0 0.9   q <=  (/i0<11>)+i1<9>
257        8 on12_x4      4.3 1.1   q <=  (/i0<9>)+i1<10>
258       --------------------------------------------------------- AND/OR 3
259        6 nao22_x1     1.2 0.9  nq <= /((i0<14>+i1<14>).i2<14>)
260       10 nao22_x4     4.3 1.3  nq <= /((i0<8> +i1<8>) .i2<9>)
261        6 noa22_x1     1.2 0.9  nq <= /((i0<14>.i1<14>)+i2<14>)
262       10 noa22_x4     4.3 1.3  nq <= /((i0<8> .i1<8>) +i2<9>)
263        6 ao22_x2      2.1 1.2   q <=  ((i0<8>+i1<8>).i2<9>)
264        8 ao22_x4      4.3 1.3   q <=  ((i0<8>+i1<8>).i2<9>)
265        6 oa22_x2      2.1 1.2   q <=  ((i0<8>.i1<8>)+i2<9>)
266        8 oa22_x4      4.3 1.3   q <=  ((i0<8>.i1<8>)+i2<9>)
267       --------------------------------------------------------- AND/OR 4
268        7 nao2o22_x1   1.2 1.0  nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
269       11 nao2o22_x4   4.3 1.4  nq <= /((i0<8> +i1<8>) .(i2<8> +i3<8>))
270        7 noa2a22_x1   1.2 1.0  nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
271       11 noa2a22_x4   4.3 1.4  nq <= /((i0<8> .i1<8>) +(i2<8> .i3<8>))
272        9 ao2o22_x2    2.1 1.2   q <=  ((i0<8>+i1<8>).(i2<8>+i3<8>))
273       10 ao2o22_x4    4.3 1.3   q <=  ((i0<8>+i1<8>).(i2<8>+i3<8>))
274        9 oa2a22_x2    2.1 1.2   q <=  ((i0<8>.i1<8>)+(i2<8>.i3<8>))
275       10 oa2a22_x4    4.3 1.4   q <=  ((i0<8>.i1<8>)+(i2<8>.i3<8>))
276       --------------------------------------------------------- AND/OR 5
277        7 noa2ao222_x1 0.7 1.1 nq <= /((i0<11>.i1<11>)+((i2<13>+i3<13>).i4<13>))
278       11 noa2ao222_x4 4.3 1.4 nq <= /((i0<11>.i1<11>)+((i2<11>+i3<11>).i4<11>))
279       10 oa2ao222_x2  2.1 1.2  q <=  ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
280       11 oa2ao222_x4  4.3 1.3  q <=  ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
281       --------------------------------------------------------- AND/OR 6
282       10 noa2a2a23_x1 0.8 1.2 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
283                                      +(i4<14>.i5<14>))
284       13 noa2a2a23_x4 4.3 1.3 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
285                                      +(i4<14>.i5<14>))
286       12 oa2a2a23_x2  2.1 1.4  q <=  ((i0<13>.i1<14>) +(i2<14>.i3<14>)
287                                      +(i4<14>.i5<14>))
288       13 oa2a2a23_x4  4.3 1.4  q <=  ((i0<13>.i1<14>) +(i2<14>.i3<14>)
289                                      +(i4<14>.i5<14>))
290       --------------------------------------------------------- AND/OR 7
291        9 noa3ao322_x1 0.6 1.2 nq <= /((i0<13>.i1<13>.i2<12>)
292                                      +((i3<13>+i4<13>+i5<13>).i6<13>))
293       11 noa3ao322_x4 4.3 1.4 nq <= /((i0<10>.i1<9>.i2<9>)
294                                      +((i3<9>+i4<9>+i5<9>).i6<9>))
295       10 oa3ao322_x2  2.1 1.2  q <= /((i0<10>.i1<9>.i2<9>)
296                                      +((i3<9>+i4<9>+i5<9>).i6<9>))
297       11 oa3ao322_x4  4.3 1.3  q <= /((i0<10>.i1<9>.i2<9>)
298                                      +((i3<9>+i4<9>+i5<9>).i6<9>))
299       --------------------------------------------------------- AND/OR 8
300       14 noa2a2a2a24_x1 0.6 1.4 nq <= /((i0<14>.i1<14>)+(i2<13>.i3<13>)
301                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
302       17 noa2a2a2a24_x4 4.3 1.7 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<13>)
303                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
304       15 oa2a2a2a24_x2  2.1 1.5  q <=  ((i0<14>.i1<14>)+(i2<14>.i3<13>)
305                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
306       16 oa2a2a2a24_x4  4.3 1.6  q <=  ((i0<14>.i1<14>)+(i2<14>.i3<13>)
307                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
308       ------------------------------------------------------ MULTIPLEXER
309        7 nmx2_x1      1.2 1.0  nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
310       12 nmx2_x4      4.3 1.3  nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
311        9 mx2_x2       2.1 1.1   q <=   (i0<8>./cmd<17>)+(i1<9>.cmd)
312       10 mx2_x4       4.3 1.3   q <=   (i0<8>./cmd<17>)+(i1<9>.cmd)
313       12 nmx3_x1      0.4 1.2  nq <= /((i0<9>./cmd0<15>)
314                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
315       15 nmx3_x4      4.3 1.7  nq <= /((i0<9>./cmd0<15>)
316                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
317       13 mx3_x2       2.1 1.4   q <=  ((i0<9>./cmd0<15>)
318                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
319       14 mx3_x4       4.3 1.6   q <=  ((i0<9>./cmd0<15>)
320                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
321       -------------------------------------------------------------- XOR
322        9 nxr2_x1      1.2 1.1  nq <= /(i0<21>^i1<22>)
323       11 nxr2_x4      4.3 1.2  nq <= /(i0<20>^i1<21>)
324        9 xr2_x1       1.2 1.0   q <=  (i0<21>^i1<22>)
325       12 xr2_x4       4.3 1.2   q <=  (i0<20>^i1<21>)
326       -------------------------------------------------------- FLIP-FLOP
327                                   nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
328       18 sff1_x4      4.3 1.7  IF RISE(ck<8>)
329                                    q <= i<8>
330       24 sff2_x4      4.3 1.9  IF RISE(ck<8>)
331                                    q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
332       28 sff3_x4      4.3 2.4  IF RISE(ck<8>)
333                                    q <= (i0<9>./cmd0<15>)
334                                        +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)
335       ------------------------------------------------------------ ADDER
336       16 halfadder_x2 2.1 1.2 sout <= (a<27>^b<22>)
337                       2.1 1.0 cout <= (a.b)
338       18 halfadder_x4 4.3 1.3 sout <= (a<27>^b<22>)
339                       4.3 1.1 cout <= (a.b)
340       20 fulladder_x2 2.1 1.8 sout <= (a*<28>^b*<28>^cin*<19>)
341                       2.1 1.4 cout <= (a*.b*+a*.cin*+b*.cin*)
342       21 fulladder_x4 4.3 2.2 sout <= (a*<28>^b*<28>^cin*<19>)
343                       4.3 1.5 cout <= (a*.b*+a*.cin*+b*.cin*)
344       ---------------------------------------------------------- SPECIAL
345        3 zero_x0       0   0  nq <= '0'
346        3 one_x0        0   0   q <= '1'
347        2 tie_x0        0   0  Body tie cell
348        1 rowend_x0     0   0  Empty cell
349       ==================================================================
350
351

NEW CELLS

353       It is possible to add new cells in the library just by providing the  3
354       files  .ap,  .al  and  .vbe in the standard cell directory.  The layout
355       view can be created with the symbolic editor graal.  The physical  out‐
356       line  is given above.  The net-list view can be automatically generated
357       with the lynx extractor.  The behavioral view must be  written  by  the
358       designer  and  checked  with the yagle functional abstractor.  The file
359       must contain the generic fields in order to be used by the  logic  syn‐
360       thesis  tools  and the I/Os terminals must be in the same order (alpha‐
361       betic) in the .vbe and .al files.
362
363       If you develop new  cells,  please  send  the  corresponding  files  to
364       alliance-users@asim.lip6.fr
365
366

VHDL FILES

368       You can find below the commented VHDL GENERIC for the na2_x4 cell.
369       ENTITY na2_x4 IS
370       GENERIC (
371         CONSTANT area          : NATURAL := 1750; -- lamba * lambda
372         CONSTANT transistors   : NATURAL := 10;   -- number of
373         CONSTANT cin_i0        : NATURAL := 10;   -- femto Farad for i0
374         CONSTANT cin_i1        : NATURAL := 10;   -- femto Farad for i1
375         CONSTANT tplh_i1_nq    : NATURAL := 606;  -- propag. time in pico-sec
376                                                   -- from i1 falling
377                                                   -- to   nq rizing
378         CONSTANT rup_i1_nq     : NATURAL := 890;  -- resitance in Ohms when nq
379                                                   -- rizing due to i1 change
380         CONSTANT tphl_i1_nq    : NATURAL := 349;  -- propag time when nq falls
381         CONSTANT rdown_i1_nq   : NATURAL := 800;  -- resist when nq falls
382         CONSTANT tplh_i0_nq    : NATURAL := 557;  -- idem for i0
383         CONSTANT rup_i0_nq     : NATURAL := 890;
384         CONSTANT tphl_i0_nq    : NATURAL := 408;
385         CONSTANT rdown_i0_nq   : NATURAL := 800
386       );
387       PORT (
388         i0     : in  BIT;
389         i1     : in  BIT;
390         nq     : out BIT;
391         vdd    : in  BIT;
392         vss    : in  BIT
393       );
394
395

SEE ALSO

397       MBK_CATA_LIB   (1),  catal(1),  ocp(1),  nero(1),  cougar(1),  boom(1),
398       loon(1), boog(1), genlib(1), ap(5), al(5), vbe(5)
399
400
401
402
403ASIM/LIP6                      October 19, 1999                       SXLIB(5)
Impressum