1AS(1)                        GNU Development Tools                       AS(1)
2
3
4

NAME

6       AS - the portable GNU assembler.
7

SYNOPSIS

9       as [-a[cdghlns][=file]] [--alternate] [-D]
10        [--compress-debug-sections]  [--nocompress-debug-sections]
11        [--debug-prefix-map old=new]
12        [--defsym sym=val] [-f] [-g] [--gstabs]
13        [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14        [--help] [-I dir] [-J]
15        [-K] [-L] [--listing-lhs-width=NUM]
16        [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
17        [--listing-cont-lines=NUM] [--keep-locals]
18        [--no-pad-sections]
19        [-o objfile] [-R]
20        [--hash-size=NUM] [--reduce-memory-overheads]
21        [--statistics]
22        [-v] [-version] [--version]
23        [-W] [--warn] [--fatal-warnings] [-w] [-x]
24        [-Z] [@FILE]
25        [--sectname-subst] [--size-check=[error|warning]]
26        [--elf-stt-common=[no|yes]]
27        [--generate-missing-build-notes=[no|yes]]
28        [--target-help] [target-options]
29        [--|files ...]
30

TARGET

32       Target AArch64 options:
33          [-EB|-EL]
34          [-mabi=ABI]
35
36       Target Alpha options:
37          [-mcpu]
38          [-mdebug | -no-mdebug]
39          [-replace | -noreplace]
40          [-relax] [-g] [-Gsize]
41          [-F] [-32addr]
42
43       Target ARC options:
44          [-mcpu=cpu]
45          [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
46          [-mcode-density]
47          [-mrelax]
48          [-EB|-EL]
49
50       Target ARM options:
51          [-mcpu=processor[+extension...]]
52          [-march=architecture[+extension...]]
53          [-mfpu=floating-point-format]
54          [-mfloat-abi=abi]
55          [-meabi=ver]
56          [-mthumb]
57          [-EB|-EL]
58          [-mapcs-32|-mapcs-26|-mapcs-float|
59           -mapcs-reentrant]
60          [-mthumb-interwork] [-k]
61
62       Target Blackfin options:
63          [-mcpu=processor[-sirevision]]
64          [-mfdpic]
65          [-mno-fdpic]
66          [-mnopic]
67
68       Target CRIS options:
69          [--underscore | --no-underscore]
70          [--pic] [-N]
71          [--emulation=criself | --emulation=crisaout]
72          [--march=v0_v10 | --march=v10 | --march=v32 |
73       --march=common_v10_v32]
74
75       Target C-SKY options:
76          [-march=arch] [-mcpu=cpu]
77          [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
78          [-fpic] [-pic]
79          [-mljump] [-mno-ljump]
80          [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
81          [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
82          [-mnolrw ] [-mno-lrw]
83          [-melrw] [-mno-elrw]
84          [-mlaf ] [-mliterals-after-func]
85          [-mno-laf] [-mno-literals-after-func]
86          [-mlabr] [-mliterals-after-br]
87          [-mno-labr] [-mnoliterals-after-br]
88          [-mistack] [-mno-istack]
89          [-mhard-float] [-mmp] [-mcp] [-mcache]
90          [-msecurity] [-mtrust]
91          [-mdsp] [-medsp] [-mvdsp]
92
93       Target D10V options:
94          [-O]
95
96       Target D30V options:
97          [-O|-n|-N]
98
99       Target EPIPHANY options:
100          [-mepiphany|-mepiphany16]
101
102       Target H8/300 options:
103          [-h-tick-hex]
104
105       Target i386 options:
106          [--32|--x32|--64] [-n]
107          [-march=CPU[+EXTENSION...]] [-mtune=CPU]
108
109       Target IA-64 options:
110          [-mconstant-gp|-mauto-pic]
111          [-milp32|-milp64|-mlp64|-mp64]
112          [-mle|mbe]
113          [-mtune=itanium1|-mtune=itanium2]
114          [-munwind-check=warning|-munwind-check=error]
115          [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
116          [-x|-xexplicit] [-xauto] [-xdebug]
117
118       Target IP2K options:
119          [-mip2022|-mip2022ext]
120
121       Target M32C options:
122          [-m32c|-m16c] [-relax] [-h-tick-hex]
123
124       Target M32R options:
125          [--m32rx|--[no-]warn-explicit-parallel-conflicts|
126          --W[n]p]
127
128       Target M680X0 options:
129          [-l] [-m68000|-m68010|-m68020|...]
130
131       Target M68HC11 options:
132          [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
133          [-mshort|-mlong]
134          [-mshort-double|-mlong-double]
135          [--force-long-branches] [--short-branches]
136          [--strict-direct-mode] [--print-insn-syntax]
137          [--print-opcodes] [--generate-example]
138
139       Target MCORE options:
140          [-jsri2bsr] [-sifilter] [-relax]
141          [-mcpu=[210|340]]
142
143       Target Meta options:
144          [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
145
146       Target MIPS options:
147          [-nocpp] [-EL] [-EB] [-O[optimization level]]
148          [-g[debug level]] [-G num] [-KPIC] [-call_shared]
149          [-non_shared] [-xgot [-mvxworks-pic]
150          [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
151          [-mfp64] [-mgp64] [-mfpxx]
152          [-modd-spreg] [-mno-odd-spreg]
153          [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
154          [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
155          [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
156          [-mips64r3] [-mips64r5] [-mips64r6]
157          [-construct-floats] [-no-construct-floats]
158          [-mignore-branch-isa] [-mno-ignore-branch-isa]
159          [-mnan=encoding]
160          [-trap] [-no-break] [-break] [-no-trap]
161          [-mips16] [-no-mips16]
162          [-mmips16e2] [-mno-mips16e2]
163          [-mmicromips] [-mno-micromips]
164          [-msmartmips] [-mno-smartmips]
165          [-mips3d] [-no-mips3d]
166          [-mdmx] [-no-mdmx]
167          [-mdsp] [-mno-dsp]
168          [-mdspr2] [-mno-dspr2]
169          [-mdspr3] [-mno-dspr3]
170          [-mmsa] [-mno-msa]
171          [-mxpa] [-mno-xpa]
172          [-mmt] [-mno-mt]
173          [-mmcu] [-mno-mcu]
174          [-mcrc] [-mno-crc]
175          [-mginv] [-mno-ginv]
176          [-mloongson-mmi] [-mno-loongson-mmi]
177          [-mloongson-cam] [-mno-loongson-cam]
178          [-mloongson-ext] [-mno-loongson-ext]
179          [-mloongson-ext2] [-mno-loongson-ext2]
180          [-minsn32] [-mno-insn32]
181          [-mfix7000] [-mno-fix7000]
182          [-mfix-rm7000] [-mno-fix-rm7000]
183          [-mfix-vr4120] [-mno-fix-vr4120]
184          [-mfix-vr4130] [-mno-fix-vr4130]
185          [-mfix-r5900] [-mno-fix-r5900]
186          [-mdebug] [-no-mdebug]
187          [-mpdr] [-mno-pdr]
188
189       Target MMIX options:
190          [--fixed-special-register-names] [--globalize-symbols]
191          [--gnu-syntax] [--relax] [--no-predefined-symbols]
192          [--no-expand] [--no-merge-gregs] [-x]
193          [--linker-allocated-gregs]
194
195       Target Nios II options:
196          [-relax-all] [-relax-section] [-no-relax]
197          [-EB] [-EL]
198
199       Target NDS32 options:
200           [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
201           [-misa=isa] [-mabi=abi] [-mall-ext]
202           [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
203           [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
204           [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
205           [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
206           [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
207           [-mb2bb]
208
209       Target PDP11 options:
210          [-mpic|-mno-pic] [-mall] [-mno-extensions]
211          [-mextension|-mno-extension]
212          [-mcpu] [-mmachine]
213
214       Target picoJava options:
215          [-mb|-me]
216
217       Target PowerPC options:
218          [-a32|-a64]
219          [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
220           -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
221           -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
222           -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
223           -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
224           -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
225          [-many] [-maltivec|-mvsx|-mhtm|-mvle]
226          [-mregnames|-mno-regnames]
227          [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
228          [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
229          [-msolaris|-mno-solaris]
230          [-nops=count]
231
232       Target PRU options:
233          [-link-relax]
234          [-mnolink-relax]
235          [-mno-warn-regname-label]
236
237       Target RISC-V options:
238          [-fpic|-fPIC|-fno-pic]
239          [-march=ISA]
240          [-mabi=ABI]
241
242       Target RL78 options:
243          [-mg10]
244          [-m32bit-doubles|-m64bit-doubles]
245
246       Target RX options:
247          [-mlittle-endian|-mbig-endian]
248          [-m32bit-doubles|-m64bit-doubles]
249          [-muse-conventional-section-names]
250          [-msmall-data-limit]
251          [-mpid]
252          [-mrelax]
253          [-mint-register=number]
254          [-mgcc-abi|-mrx-abi]
255
256       Target s390 options:
257          [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
258          [-mregnames|-mno-regnames]
259          [-mwarn-areg-zero]
260
261       Target SCORE options:
262          [-EB][-EL][-FIXDD][-NWARN]
263          [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
264          [-march=score7][-march=score3]
265          [-USE_R1][-KPIC][-O0][-G num][-V]
266
267       Target SPARC options:
268          [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
269           -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
270           -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
271           -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
272           -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
273           -Asparcvisr|-Asparc5]
274          [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
275           -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
276           -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
277           -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
278           -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
279           -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
280           -bump]
281          [-32|-64]
282          [--enforce-aligned-data][--dcti-couples-detect]
283
284       Target TIC54X options:
285        [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
286        [-merrors-to-file <filename>|-me <filename>]
287
288       Target TIC6X options:
289          [-march=arch] [-mbig-endian|-mlittle-endian]
290          [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
291          [-mpic|-mno-pic]
292
293       Target TILE-Gx options:
294          [-m32|-m64][-EB][-EL]
295
296       Target Visium options:
297          [-mtune=arch]
298
299       Target Xtensa options:
300        [--[no-]text-section-literals] [--[no-]auto-litpools]
301        [--[no-]absolute-literals]
302        [--[no-]target-align] [--[no-]longcalls]
303        [--[no-]transform]
304        [--rename-section oldname=newname]
305        [--[no-]trampolines]
306
307       Target Z80 options:
308         [-z80] [-r800]
309         [ -ignore-undocumented-instructions] [-Wnud]
310         [ -ignore-unportable-instructions] [-Wnup]
311         [ -warn-undocumented-instructions] [-Wud]
312         [ -warn-unportable-instructions] [-Wup]
313         [ -forbid-undocumented-instructions] [-Fud]
314         [ -forbid-unportable-instructions] [-Fup]
315

DESCRIPTION

317       GNU as is really a family of assemblers.  If you use (or have used) the
318       GNU assembler on one architecture, you should find a fairly similar
319       environment when you use it on another architecture.  Each version has
320       much in common with the others, including object file formats, most
321       assembler directives (often called pseudo-ops) and assembler syntax.
322
323       as is primarily intended to assemble the output of the GNU C compiler
324       "gcc" for use by the linker "ld".  Nevertheless, we've tried to make as
325       assemble correctly everything that other assemblers for the same
326       machine would assemble.  Any exceptions are documented explicitly.
327       This doesn't mean as always uses the same syntax as another assembler
328       for the same architecture; for example, we know of several incompatible
329       versions of 680x0 assembly language syntax.
330
331       Each time you run as it assembles exactly one source program.  The
332       source program is made up of one or more files.  (The standard input is
333       also a file.)
334
335       You give as a command line that has zero or more input file names.  The
336       input files are read (from left file name to right).  A command-line
337       argument (in any position) that has no special meaning is taken to be
338       an input file name.
339
340       If you give as no file names it attempts to read one input file from
341       the as standard input, which is normally your terminal.  You may have
342       to type ctl-D to tell as there is no more program to assemble.
343
344       Use -- if you need to explicitly name the standard input file in your
345       command line.
346
347       If the source is empty, as produces a small, empty object file.
348
349       as may write warnings and error messages to the standard error file
350       (usually your terminal).  This should not happen when  a compiler runs
351       as automatically.  Warnings report an assumption made so that as could
352       keep assembling a flawed program; errors report a grave problem that
353       stops the assembly.
354
355       If you are invoking as via the GNU C compiler, you can use the -Wa
356       option to pass arguments through to the assembler.  The assembler
357       arguments must be separated from each other (and the -Wa) by commas.
358       For example:
359
360               gcc -c -g -O -Wa,-alh,-L file.c
361
362       This passes two options to the assembler: -alh (emit a listing to
363       standard output with high-level and assembly source) and -L (retain
364       local symbols in the symbol table).
365
366       Usually you do not need to use this -Wa mechanism, since many compiler
367       command-line options are automatically passed to the assembler by the
368       compiler.  (You can call the GNU compiler driver with the -v option to
369       see precisely what options it passes to each compilation pass,
370       including the assembler.)
371

OPTIONS

373       @file
374           Read command-line options from file.  The options read are inserted
375           in place of the original @file option.  If file does not exist, or
376           cannot be read, then the option will be treated literally, and not
377           removed.
378
379           Options in file are separated by whitespace.  A whitespace
380           character may be included in an option by surrounding the entire
381           option in either single or double quotes.  Any character (including
382           a backslash) may be included by prefixing the character to be
383           included with a backslash.  The file may itself contain additional
384           @file options; any such options will be processed recursively.
385
386       -a[cdghlmns]
387           Turn on listings, in any of a variety of ways:
388
389           -ac omit false conditionals
390
391           -ad omit debugging directives
392
393           -ag include general information, like as version and options passed
394
395           -ah include high-level source
396
397           -al include assembly
398
399           -am include macro expansions
400
401           -an omit forms processing
402
403           -as include symbols
404
405           =file
406               set the name of the listing file
407
408           You may combine these options; for example, use -aln for assembly
409           listing without forms processing.  The =file option, if used, must
410           be the last one.  By itself, -a defaults to -ahls.
411
412       --alternate
413           Begin in alternate macro mode.
414
415       --compress-debug-sections
416           Compress DWARF debug sections using zlib with SHF_COMPRESSED from
417           the ELF ABI.  The resulting object file may not be compatible with
418           older linkers and object file utilities.  Note if compression would
419           make a given section larger then it is not compressed.
420
421       --compress-debug-sections=none
422       --compress-debug-sections=zlib
423       --compress-debug-sections=zlib-gnu
424       --compress-debug-sections=zlib-gabi
425           These options control how DWARF debug sections are compressed.
426           --compress-debug-sections=none is equivalent to
427           --nocompress-debug-sections.  --compress-debug-sections=zlib and
428           --compress-debug-sections=zlib-gabi are equivalent to
429           --compress-debug-sections.  --compress-debug-sections=zlib-gnu
430           compresses DWARF debug sections using zlib.  The debug sections are
431           renamed to begin with .zdebug.  Note if compression would make a
432           given section larger then it is not compressed nor renamed.
433
434       --nocompress-debug-sections
435           Do not compress DWARF debug sections.  This is usually the default
436           for all targets except the x86/x86_64, but a configure time option
437           can be used to override this.
438
439       -D  Ignored.  This option is accepted for script compatibility with
440           calls to other assemblers.
441
442       --debug-prefix-map old=new
443           When assembling files in directory old, record debugging
444           information describing them as in new instead.
445
446       --defsym sym=value
447           Define the symbol sym to be value before assembling the input file.
448           value must be an integer constant.  As in C, a leading 0x indicates
449           a hexadecimal value, and a leading 0 indicates an octal value.  The
450           value of the symbol can be overridden inside a source file via the
451           use of a ".set" pseudo-op.
452
453       -f  "fast"---skip whitespace and comment preprocessing (assume source
454           is compiler output).
455
456       -g
457       --gen-debug
458           Generate debugging information for each assembler source line using
459           whichever debug format is preferred by the target.  This currently
460           means either STABS, ECOFF or DWARF2.
461
462       --gstabs
463           Generate stabs debugging information for each assembler line.  This
464           may help debugging assembler code, if the debugger can handle it.
465
466       --gstabs+
467           Generate stabs debugging information for each assembler line, with
468           GNU extensions that probably only gdb can handle, and that could
469           make other debuggers crash or refuse to read your program.  This
470           may help debugging assembler code.  Currently the only GNU
471           extension is the location of the current working directory at
472           assembling time.
473
474       --gdwarf-2
475           Generate DWARF2 debugging information for each assembler line.
476           This may help debugging assembler code, if the debugger can handle
477           it.  Note---this option is only supported by some targets, not all
478           of them.
479
480       --gdwarf-sections
481           Instead of creating a .debug_line section, create a series of
482           .debug_line.foo sections where foo is the name of the corresponding
483           code section.  For example a code section called .text.func will
484           have its dwarf line number information placed into a section called
485           .debug_line.text.func.  If the code section is just called .text
486           then debug line section will still be called just .debug_line
487           without any suffix.
488
489       --size-check=error
490       --size-check=warning
491           Issue an error or warning for invalid ELF .size directive.
492
493       --elf-stt-common=no
494       --elf-stt-common=yes
495           These options control whether the ELF assembler should generate
496           common symbols with the "STT_COMMON" type.  The default can be
497           controlled by a configure option --enable-elf-stt-common.
498
499       --generate-missing-build-notes=yes
500       --generate-missing-build-notes=no
501           These options control whether the ELF assembler should generate GNU
502           Build attribute notes if none are present in the input sources.
503           The default can be controlled by the --enable-generate-build-notes
504           configure option.
505
506       --help
507           Print a summary of the command-line options and exit.
508
509       --target-help
510           Print a summary of all target specific options and exit.
511
512       -I dir
513           Add directory dir to the search list for ".include" directives.
514
515       -J  Don't warn about signed overflow.
516
517       -K  Issue warnings when difference tables altered for long
518           displacements.
519
520       -L
521       --keep-locals
522           Keep (in the symbol table) local symbols.  These symbols start with
523           system-specific local label prefixes, typically .L for ELF systems
524           or L for traditional a.out systems.
525
526       --listing-lhs-width=number
527           Set the maximum width, in words, of the output data column for an
528           assembler listing to number.
529
530       --listing-lhs-width2=number
531           Set the maximum width, in words, of the output data column for
532           continuation lines in an assembler listing to number.
533
534       --listing-rhs-width=number
535           Set the maximum width of an input source line, as displayed in a
536           listing, to number bytes.
537
538       --listing-cont-lines=number
539           Set the maximum number of lines printed in a listing for a single
540           line of input to number + 1.
541
542       --no-pad-sections
543           Stop the assembler for padding the ends of output sections to the
544           alignment of that section.  The default is to pad the sections, but
545           this can waste space which might be needed on targets which have
546           tight memory constraints.
547
548       -o objfile
549           Name the object-file output from as objfile.
550
551       -R  Fold the data section into the text section.
552
553       --hash-size=number
554           Set the default size of GAS's hash tables to a prime number close
555           to number.  Increasing this value can reduce the length of time it
556           takes the assembler to perform its tasks, at the expense of
557           increasing the assembler's memory requirements.  Similarly reducing
558           this value can reduce the memory requirements at the expense of
559           speed.
560
561       --reduce-memory-overheads
562           This option reduces GAS's memory requirements, at the expense of
563           making the assembly processes slower.  Currently this switch is a
564           synonym for --hash-size=4051, but in the future it may have other
565           effects as well.
566
567       --sectname-subst
568           Honor substitution sequences in section names.
569
570       --statistics
571           Print the maximum space (in bytes) and total time (in seconds) used
572           by assembly.
573
574       --strip-local-absolute
575           Remove local absolute symbols from the outgoing symbol table.
576
577       -v
578       -version
579           Print the as version.
580
581       --version
582           Print the as version and exit.
583
584       -W
585       --no-warn
586           Suppress warning messages.
587
588       --fatal-warnings
589           Treat warnings as errors.
590
591       --warn
592           Don't suppress warning messages or treat them as errors.
593
594       -w  Ignored.
595
596       -x  Ignored.
597
598       -Z  Generate an object file even after errors.
599
600       -- | files ...
601           Standard input, or source files to assemble.
602
603       The following options are available when as is configured for the
604       64-bit mode of the ARM Architecture (AArch64).
605
606       -EB This option specifies that the output generated by the assembler
607           should be marked as being encoded for a big-endian processor.
608
609       -EL This option specifies that the output generated by the assembler
610           should be marked as being encoded for a little-endian processor.
611
612       -mabi=abi
613           Specify which ABI the source code uses.  The recognized arguments
614           are: "ilp32" and "lp64", which decides the generated object file in
615           ELF32 and ELF64 format respectively.  The default is "lp64".
616
617       -mcpu=processor[+extension...]
618           This option specifies the target processor.  The assembler will
619           issue an error message if an attempt is made to assemble an
620           instruction which will not execute on the target processor.  The
621           following processor names are recognized: "cortex-a35",
622           "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a72",
623           "cortex-a73", "cortex-a75", "cortex-a76", "ares", "exynos-m1",
624           "falkor", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1" and
625           "xgene2".  The special name "all" may be used to allow the
626           assembler to accept instructions valid for any supported processor,
627           including all optional extensions.
628
629           In addition to the basic instruction set, the assembler can be told
630           to accept, or restrict, various extension mnemonics that extend the
631           processor.
632
633           If some implementations of a particular processor can have an
634           extension, then then those extensions are automatically enabled.
635           Consequently, you will not normally have to specify any additional
636           extensions.
637
638       -march=architecture[+extension...]
639           This option specifies the target architecture.  The assembler will
640           issue an error message if an attempt is made to assemble an
641           instruction which will not execute on the target architecture.  The
642           following architecture names are recognized: "armv8-a",
643           "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" and "armv8.5-a".
644
645           If both -mcpu and -march are specified, the assembler will use the
646           setting for -mcpu.  If neither are specified, the assembler will
647           default to -mcpu=all.
648
649           The architecture option can be extended with the same instruction
650           set extension options as the -mcpu option.  Unlike -mcpu,
651           extensions are not always enabled by default,
652
653       -mverbose-error
654           This option enables verbose error messages for AArch64 gas.  This
655           option is enabled by default.
656
657       -mno-verbose-error
658           This option disables verbose error messages in AArch64 gas.
659
660       The following options are available when as is configured for an Alpha
661       processor.
662
663       -mcpu
664           This option specifies the target processor.  If an attempt is made
665           to assemble an instruction which will not execute on the target
666           processor, the assembler may either expand the instruction as a
667           macro or issue an error message.  This option is equivalent to the
668           ".arch" directive.
669
670           The following processor names are recognized: 21064, "21064a",
671           21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
672           "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
673           "ev67", "ev68".  The special name "all" may be used to allow the
674           assembler to accept instructions valid for any Alpha processor.
675
676           In order to support existing practice in OSF/1 with respect to
677           ".arch", and existing practice within MILO (the Linux ARC
678           bootloader), the numbered processor names (e.g. 21064) enable the
679           processor-specific PALcode instructions, while the "electro-vlasic"
680           names (e.g. "ev4") do not.
681
682       -mdebug
683       -no-mdebug
684           Enables or disables the generation of ".mdebug" encapsulation for
685           stabs directives and procedure descriptors.  The default is to
686           automatically enable ".mdebug" when the first stabs directive is
687           seen.
688
689       -relax
690           This option forces all relocations to be put into the object file,
691           instead of saving space and resolving some relocations at assembly
692           time.  Note that this option does not propagate all symbol
693           arithmetic into the object file, because not all symbol arithmetic
694           can be represented.  However, the option can still be useful in
695           specific applications.
696
697       -replace
698       -noreplace
699           Enables or disables the optimization of procedure calls, both at
700           assemblage and at link time.  These options are only available for
701           VMS targets and "-replace" is the default.  See section 1.4.1 of
702           the OpenVMS Linker Utility Manual.
703
704       -g  This option is used when the compiler generates debug information.
705           When gcc is using mips-tfile to generate debug information for
706           ECOFF, local labels must be passed through to the object file.
707           Otherwise this option has no effect.
708
709       -Gsize
710           A local common symbol larger than size is placed in ".bss", while
711           smaller symbols are placed in ".sbss".
712
713       -F
714       -32addr
715           These options are ignored for backward compatibility.
716
717       The following options are available when as is configured for an ARC
718       processor.
719
720       -mcpu=cpu
721           This option selects the core processor variant.
722
723       -EB | -EL
724           Select either big-endian (-EB) or little-endian (-EL) output.
725
726       -mcode-density
727           Enable Code Density extenssion instructions.
728
729       The following options are available when as is configured for the ARM
730       processor family.
731
732       -mcpu=processor[+extension...]
733           Specify which ARM processor variant is the target.
734
735       -march=architecture[+extension...]
736           Specify which ARM architecture variant is used by the target.
737
738       -mfpu=floating-point-format
739           Select which Floating Point architecture is the target.
740
741       -mfloat-abi=abi
742           Select which floating point ABI is in use.
743
744       -mthumb
745           Enable Thumb only instruction decoding.
746
747       -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
748           Select which procedure calling convention is in use.
749
750       -EB | -EL
751           Select either big-endian (-EB) or little-endian (-EL) output.
752
753       -mthumb-interwork
754           Specify that the code has been generated with interworking between
755           Thumb and ARM code in mind.
756
757       -mccs
758           Turns on CodeComposer Studio assembly syntax compatibility mode.
759
760       -k  Specify that PIC code has been generated.
761
762       The following options are available when as is configured for the
763       Blackfin processor family.
764
765       -mcpu=processor[-sirevision]
766           This option specifies the target processor.  The optional
767           sirevision is not used in assembler.  It's here such that GCC can
768           easily pass down its "-mcpu=" option.  The assembler will issue an
769           error message if an attempt is made to assemble an instruction
770           which will not execute on the target processor.  The following
771           processor names are recognized: "bf504", "bf506", "bf512", "bf514",
772           "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
773           "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
774           implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
775           "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
776           "bf549", "bf549m", "bf561", and "bf592".
777
778       -mfdpic
779           Assemble for the FDPIC ABI.
780
781       -mno-fdpic
782       -mnopic
783           Disable -mfdpic.
784
785       See the info pages for documentation of the CRIS-specific options.
786
787       The following options are available when as is configured for the C-SKY
788       processor family.
789
790       -march=archname
791           Assemble for architecture archname.  The --help option lists valid
792           values for archname.
793
794       -mcpu=cpuname
795           Assemble for architecture cpuname.  The --help option lists valid
796           values for cpuname.
797
798       -EL
799       -mlittle-endian
800           Generate little-endian output.
801
802       -EB
803       -mbig-endian
804           Generate big-endian output.
805
806       -fpic
807       -pic
808           Generate position-independent code.
809
810       -mljump
811       -mno-ljump
812           Enable/disable transformation of the short branch instructions
813           "jbf", "jbt", and "jbr" to "jmpi".  This option is for V2
814           processors only.  It is ignored on CK801 and CK802 targets, which
815           do not support the "jmpi" instruction, and is enabled by default
816           for other processors.
817
818       -mbranch-stub
819       -mno-branch-stub
820           Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
821           instructions to the linker.
822
823           This option is only available for bare-metal C-SKY V2 ELF targets,
824           where it is enabled by default.  It cannot be used in code that
825           will be dynamically linked against shared libraries.
826
827       -force2bsr
828       -mforce2bsr
829       -no-force2bsr
830       -mno-force2bsr
831           Enable/disable transformation of "jbsr" instructions to "bsr".
832           This option is always enabled (and -mno-force2bsr is ignored) for
833           CK801/CK802 targets.  It is also always enabled when -mbranch-stub
834           is in effect.
835
836       -jsri2bsr
837       -mjsri2bsr
838       -no-jsri2bsr
839       -mno-jsri2bsr
840           Enable/disable transformation of "jsri" instructions to "bsr".
841           This option is enabled by default.
842
843       -mnolrw
844       -mno-lrw
845           Enable/disable transformation of "lrw" instructions into a
846           "movih"/"ori" pair.
847
848       -melrw
849       -mno-elrw
850           Enable/disable extended "lrw" instructions.  This option is enabled
851           by default for CK800-series processors.
852
853       -mlaf
854       -mliterals-after-func
855       -mno-laf
856       -mno-literals-after-func
857           Enable/disable placement of literal pools after each function.
858
859       -mlabr
860       -mliterals-after-br
861       -mno-labr
862       -mnoliterals-after-br
863           Enable/disable placement of literal pools after unconditional
864           branches.  This option is enabled by default.
865
866       -mistack
867       -mno-istack
868           Enable/disable interrupt stack instructions.  This option is
869           enabled by default on CK801, CK802, and CK802 processors.
870
871       The following options explicitly enable certain optional instructions.
872       These features are also enabled implicitly by using "-mcpu=" to specify
873       a processor that supports it.
874
875       -mhard-float
876           Enable hard float instructions.
877
878       -mmp
879           Enable multiprocessor instructions.
880
881       -mcp
882           Enable coprocessor instructions.
883
884       -mcache
885           Enable cache prefetch instruction.
886
887       -msecurity
888           Enable C-SKY security instructions.
889
890       -mtrust
891           Enable C-SKY trust instructions.
892
893       -mdsp
894           Enable DSP instructions.
895
896       -medsp
897           Enable enhanced DSP instructions.
898
899       -mvdsp
900           Enable vector DSP instructions.
901
902       The following options are available when as is configured for an
903       Epiphany processor.
904
905       -mepiphany
906           Specifies that the both 32 and 16 bit instructions are allowed.
907           This is the default behavior.
908
909       -mepiphany16
910           Restricts the permitted instructions to just the 16 bit set.
911
912       The following options are available when as is configured for an H8/300
913       processor.  @chapter H8/300 Dependent Features
914
915   Options
916       The Renesas H8/300 version of "as" has one machine-dependent option:
917
918       -h-tick-hex
919           Support H'00 style hex constants in addition to 0x00 style.
920
921       -mach=name
922           Sets the H8300 machine variant.  The following machine names are
923           recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
924           "h8300sxn".
925
926       The following options are available when as is configured for an i386
927       processor.
928
929       --32 | --x32 | --64
930           Select the word size, either 32 bits or 64 bits.  --32 implies
931           Intel i386 architecture, while --x32 and --64 imply AMD x86-64
932           architecture with 32-bit or 64-bit word-size respectively.
933
934           These options are only available with the ELF object file format,
935           and require that the necessary BFD support has been included (on a
936           32-bit platform you have to add --enable-64-bit-bfd to configure
937           enable 64-bit usage and use x86-64 as target platform).
938
939       -n  By default, x86 GAS replaces multiple nop instructions used for
940           alignment within code sections with multi-byte nop instructions
941           such as leal 0(%esi,1),%esi.  This switch disables the optimization
942           if a single byte nop (0x90) is explicitly specified as the fill
943           byte for alignment.
944
945       --divide
946           On SVR4-derived platforms, the character / is treated as a comment
947           character, which means that it cannot be used in expressions.  The
948           --divide option turns / into a normal character.  This does not
949           disable / at the beginning of a line starting a comment, or affect
950           using # for starting a comment.
951
952       -march=CPU[+EXTENSION...]
953           This option specifies the target processor.  The assembler will
954           issue an error message if an attempt is made to assemble an
955           instruction which will not execute on the target processor.  The
956           following processor names are recognized: "i8086", "i186", "i286",
957           "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
958           "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
959           "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
960           "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
961           "bdver3", "bdver4", "znver1", "znver2", "btver1", "btver2",
962           "generic32" and "generic64".
963
964           In addition to the basic instruction set, the assembler can be told
965           to accept various extension mnemonics.  For example,
966           "-march=i686+sse4+vmx" extends i686 with sse4 and vmx.  The
967           following extensions are currently supported: 8087, 287, 387, 687,
968           "no87", "no287", "no387", "no687", "cmov", "nocmov", "fxsr",
969           "nofxsr", "mmx", "nommx", "sse", "sse2", "sse3", "ssse3", "sse4.1",
970           "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nossse3",
971           "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2", "noavx", "noavx2",
972           "adx", "rdseed", "prfchw", "smap", "mpx", "sha", "rdpid",
973           "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq", "prefetchwt1",
974           "clflushopt", "se1", "clwb", "movdiri", "movdir64b", "avx512f",
975           "avx512cd", "avx512er", "avx512pf", "avx512vl", "avx512bw",
976           "avx512dq", "avx512ifma", "avx512vbmi", "avx512_4fmaps",
977           "avx512_4vnniw", "avx512_vpopcntdq", "avx512_vbmi2", "avx512_vnni",
978           "avx512_bitalg", "noavx512f", "noavx512cd", "noavx512er",
979           "noavx512pf", "noavx512vl", "noavx512bw", "noavx512dq",
980           "noavx512ifma", "noavx512vbmi", "noavx512_4fmaps",
981           "noavx512_4vnniw", "noavx512_vpopcntdq", "noavx512_vbmi2",
982           "noavx512_vnni", "noavx512_bitalg", "vmx", "vmfunc", "smx",
983           "xsave", "xsaveopt", "xsavec", "xsaves", "aes", "pclmul",
984           "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe", "ept",
985           "lzcnt", "hle", "rtm", "invpcid", "clflush", "mwaitx", "clzero",
986           "wbnoinvd", "pconfig", "waitpkg", "cldemote", "lwp", "fma4", "xop",
987           "cx16", "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5",
988           "svme", "abm" and "padlock".  Note that rather than extending a
989           basic instruction set, the extension mnemonics starting with "no"
990           revoke the respective functionality.
991
992           When the ".arch" directive is used with -march, the ".arch"
993           directive will take precedent.
994
995       -mtune=CPU
996           This option specifies a processor to optimize for. When used in
997           conjunction with the -march option, only instructions of the
998           processor specified by the -march option will be generated.
999
1000           Valid CPU values are identical to the processor list of -march=CPU.
1001
1002       -msse2avx
1003           This option specifies that the assembler should encode SSE
1004           instructions with VEX prefix.
1005
1006       -msse-check=none
1007       -msse-check=warning
1008       -msse-check=error
1009           These options control if the assembler should check SSE
1010           instructions.  -msse-check=none will make the assembler not to
1011           check SSE instructions,  which is the default.  -msse-check=warning
1012           will make the assembler issue a warning for any SSE instruction.
1013           -msse-check=error will make the assembler issue an error for any
1014           SSE instruction.
1015
1016       -mavxscalar=128
1017       -mavxscalar=256
1018           These options control how the assembler should encode scalar AVX
1019           instructions.  -mavxscalar=128 will encode scalar AVX instructions
1020           with 128bit vector length, which is the default.  -mavxscalar=256
1021           will encode scalar AVX instructions with 256bit vector length.
1022
1023       -mvexwig=0
1024       -mvexwig=1
1025           These options control how the assembler should encode VEX.W-ignored
1026           (WIG) VEX instructions.  -mvexwig=0 will encode WIG VEX
1027           instructions with vex.w = 0, which is the default.  -mvexwig=1 will
1028           encode WIG EVEX instructions with vex.w = 1.
1029
1030       -mevexlig=128
1031       -mevexlig=256
1032       -mevexlig=512
1033           These options control how the assembler should encode length-
1034           ignored (LIG) EVEX instructions.  -mevexlig=128 will encode LIG
1035           EVEX instructions with 128bit vector length, which is the default.
1036           -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1037           with 256bit and 512bit vector length, respectively.
1038
1039       -mevexwig=0
1040       -mevexwig=1
1041           These options control how the assembler should encode w-ignored
1042           (WIG) EVEX instructions.  -mevexwig=0 will encode WIG EVEX
1043           instructions with evex.w = 0, which is the default.  -mevexwig=1
1044           will encode WIG EVEX instructions with evex.w = 1.
1045
1046       -mmnemonic=att
1047       -mmnemonic=intel
1048           This option specifies instruction mnemonic for matching
1049           instructions.  The ".att_mnemonic" and ".intel_mnemonic" directives
1050           will take precedent.
1051
1052       -msyntax=att
1053       -msyntax=intel
1054           This option specifies instruction syntax when processing
1055           instructions.  The ".att_syntax" and ".intel_syntax" directives
1056           will take precedent.
1057
1058       -mnaked-reg
1059           This option specifies that registers don't require a % prefix.  The
1060           ".att_syntax" and ".intel_syntax" directives will take precedent.
1061
1062       -madd-bnd-prefix
1063           This option forces the assembler to add BND prefix to all branches,
1064           even if such prefix was not explicitly specified in the source
1065           code.
1066
1067       -mno-shared
1068           On ELF target, the assembler normally optimizes out non-PLT
1069           relocations against defined non-weak global branch targets with
1070           default visibility.  The -mshared option tells the assembler to
1071           generate code which may go into a shared library where all non-weak
1072           global branch targets with default visibility can be preempted.
1073           The resulting code is slightly bigger.  This option only affects
1074           the handling of branch instructions.
1075
1076       -mbig-obj
1077           On x86-64 PE/COFF target this option forces the use of big object
1078           file format, which allows more than 32768 sections.
1079
1080       -momit-lock-prefix=no
1081       -momit-lock-prefix=yes
1082           These options control how the assembler should encode lock prefix.
1083           This option is intended as a workaround for processors, that fail
1084           on lock prefix. This option can only be safely used with single-
1085           core, single-thread computers -momit-lock-prefix=yes will omit all
1086           lock prefixes.  -momit-lock-prefix=no will encode lock prefix as
1087           usual, which is the default.
1088
1089       -mfence-as-lock-add=no
1090       -mfence-as-lock-add=yes
1091           These options control how the assembler should encode lfence,
1092           mfence and sfence.  -mfence-as-lock-add=yes will encode lfence,
1093           mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1094           addl $0x0, (%esp) in 32-bit mode.  -mfence-as-lock-add=no will
1095           encode lfence, mfence and sfence as usual, which is the default.
1096
1097       -mrelax-relocations=no
1098       -mrelax-relocations=yes
1099           These options control whether the assembler should generate relax
1100           relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1101           and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1102           -mrelax-relocations=yes will generate relax relocations.
1103           -mrelax-relocations=no will not generate relax relocations.  The
1104           default can be controlled by a configure option
1105           --enable-x86-relax-relocations.
1106
1107       -mx86-used-note=no
1108       -mx86-used-note=yes
1109           These options control whether the assembler should generate
1110           GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1111           property notes.  The default can be controlled by the
1112           --enable-x86-used-note configure option.
1113
1114       -mevexrcig=rne
1115       -mevexrcig=rd
1116       -mevexrcig=ru
1117       -mevexrcig=rz
1118           These options control how the assembler should encode SAE-only EVEX
1119           instructions.  -mevexrcig=rne will encode RC bits of EVEX
1120           instruction with 00, which is the default.  -mevexrcig=rd,
1121           -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1122           instructions with 01, 10 and 11 RC bits, respectively.
1123
1124       -mamd64
1125       -mintel64
1126           This option specifies that the assembler should accept only AMD64
1127           or Intel64 ISA in 64-bit mode.  The default is to accept both.
1128
1129       -O0 | -O | -O1 | -O2 | -Os
1130           Optimize instruction encoding with smaller instruction size.  -O
1131           and -O1 encode 64-bit register load instructions with 64-bit
1132           immediate as 32-bit register load instructions with 31-bit or
1133           32-bits immediates and encode 64-bit register clearing instructions
1134           with 32-bit register clearing instructions.  -O2 includes -O1
1135           optimization plus encodes 256-bit and 512-bit vector register
1136           clearing instructions with 128-bit vector register clearing
1137           instructions.  -Os includes -O2 optimization plus encodes 16-bit,
1138           32-bit and 64-bit register tests with immediate as 8-bit register
1139           test with immediate.  -O0 turns off this optimization.
1140
1141       The following options are available when as is configured for the
1142       Ubicom IP2K series.
1143
1144       -mip2022ext
1145           Specifies that the extended IP2022 instructions are allowed.
1146
1147       -mip2022
1148           Restores the default behaviour, which restricts the permitted
1149           instructions to just the basic IP2022 ones.
1150
1151       The following options are available when as is configured for the
1152       Renesas M32C and M16C processors.
1153
1154       -m32c
1155           Assemble M32C instructions.
1156
1157       -m16c
1158           Assemble M16C instructions (the default).
1159
1160       -relax
1161           Enable support for link-time relaxations.
1162
1163       -h-tick-hex
1164           Support H'00 style hex constants in addition to 0x00 style.
1165
1166       The following options are available when as is configured for the
1167       Renesas M32R (formerly Mitsubishi M32R) series.
1168
1169       --m32rx
1170           Specify which processor in the M32R family is the target.  The
1171           default is normally the M32R, but this option changes it to the
1172           M32RX.
1173
1174       --warn-explicit-parallel-conflicts or --Wp
1175           Produce warning messages when questionable parallel constructs are
1176           encountered.
1177
1178       --no-warn-explicit-parallel-conflicts or --Wnp
1179           Do not produce warning messages when questionable parallel
1180           constructs are encountered.
1181
1182       The following options are available when as is configured for the
1183       Motorola 68000 series.
1184
1185       -l  Shorten references to undefined symbols, to one word instead of
1186           two.
1187
1188       -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1189       | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1190       | -m68333 | -m68340 | -mcpu32 | -m5200
1191           Specify what processor in the 68000 family is the target.  The
1192           default is normally the 68020, but this can be changed at
1193           configuration time.
1194
1195       -m68881 | -m68882 | -mno-68881 | -mno-68882
1196           The target machine does (or does not) have a floating-point
1197           coprocessor.  The default is to assume a coprocessor for 68020,
1198           68030, and cpu32.  Although the basic 68000 is not compatible with
1199           the 68881, a combination of the two can be specified, since it's
1200           possible to do emulation of the coprocessor instructions with the
1201           main processor.
1202
1203       -m68851 | -mno-68851
1204           The target machine does (or does not) have a memory-management unit
1205           coprocessor.  The default is to assume an MMU for 68020 and up.
1206
1207       The following options are available when as is configured for an Altera
1208       Nios II processor.
1209
1210       -relax-section
1211           Replace identified out-of-range branches with PC-relative "jmp"
1212           sequences when possible.  The generated code sequences are suitable
1213           for use in position-independent code, but there is a practical
1214           limit on the extended branch range because of the length of the
1215           sequences.  This option is the default.
1216
1217       -relax-all
1218           Replace branch instructions not determinable to be in range and all
1219           call instructions with "jmp" and "callr" sequences (respectively).
1220           This option generates absolute relocations against the target
1221           symbols and is not appropriate for position-independent code.
1222
1223       -no-relax
1224           Do not replace any branches or calls.
1225
1226       -EB Generate big-endian output.
1227
1228       -EL Generate little-endian output.  This is the default.
1229
1230       -march=architecture
1231           This option specifies the target architecture.  The assembler
1232           issues an error message if an attempt is made to assemble an
1233           instruction which will not execute on the target architecture.  The
1234           following architecture names are recognized: "r1", "r2".  The
1235           default is "r1".
1236
1237       The following options are available when as is configured for a PRU
1238       processor.
1239
1240       -mlink-relax
1241           Assume that LD would optimize LDI32 instructions by checking the
1242           upper 16 bits of the expression. If they are all zeros, then LD
1243           would shorten the LDI32 instruction to a single LDI. In such case
1244           "as" will output DIFF relocations for diff expressions.
1245
1246       -mno-link-relax
1247           Assume that LD would not optimize LDI32 instructions. As a
1248           consequence, DIFF relocations will not be emitted.
1249
1250       -mno-warn-regname-label
1251           Do not warn if a label name matches a register name. Usually
1252           assembler programmers will want this warning to be emitted. C
1253           compilers may want to turn this off.
1254
1255       The following options are available when as is configured for a MIPS
1256       processor.
1257
1258       -G num
1259           This option sets the largest size of an object that can be
1260           referenced implicitly with the "gp" register.  It is only accepted
1261           for targets that use ECOFF format, such as a DECstation running
1262           Ultrix.  The default value is 8.
1263
1264       -EB Generate "big endian" format output.
1265
1266       -EL Generate "little endian" format output.
1267
1268       -mips1
1269       -mips2
1270       -mips3
1271       -mips4
1272       -mips5
1273       -mips32
1274       -mips32r2
1275       -mips32r3
1276       -mips32r5
1277       -mips32r6
1278       -mips64
1279       -mips64r2
1280       -mips64r3
1281       -mips64r5
1282       -mips64r6
1283           Generate code for a particular MIPS Instruction Set Architecture
1284           level.  -mips1 is an alias for -march=r3000, -mips2 is an alias for
1285           -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1286           alias for -march=r8000.  -mips5, -mips32, -mips32r2, -mips32r3,
1287           -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1288           -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1289           MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1290           MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1291           Release 6 ISA processors, respectively.
1292
1293       -march=cpu
1294           Generate code for a particular MIPS CPU.
1295
1296       -mtune=cpu
1297           Schedule and tune for a particular MIPS CPU.
1298
1299       -mfix7000
1300       -mno-fix7000
1301           Cause nops to be inserted if the read of the destination register
1302           of an mfhi or mflo instruction occurs in the following two
1303           instructions.
1304
1305       -mfix-rm7000
1306       -mno-fix-rm7000
1307           Cause nops to be inserted if a dmult or dmultu instruction is
1308           followed by a load instruction.
1309
1310       -mfix-r5900
1311       -mno-fix-r5900
1312           Do not attempt to schedule the preceding instruction into the delay
1313           slot of a branch instruction placed at the end of a short loop of
1314           six instructions or fewer and always schedule a "nop" instruction
1315           there instead.  The short loop bug under certain conditions causes
1316           loops to execute only once or twice, due to a hardware bug in the
1317           R5900 chip.
1318
1319       -mdebug
1320       -no-mdebug
1321           Cause stabs-style debugging output to go into an ECOFF-style
1322           .mdebug section instead of the standard ELF .stabs sections.
1323
1324       -mpdr
1325       -mno-pdr
1326           Control generation of ".pdr" sections.
1327
1328       -mgp32
1329       -mfp32
1330           The register sizes are normally inferred from the ISA and ABI, but
1331           these flags force a certain group of registers to be treated as 32
1332           bits wide at all times.  -mgp32 controls the size of general-
1333           purpose registers and -mfp32 controls the size of floating-point
1334           registers.
1335
1336       -mgp64
1337       -mfp64
1338           The register sizes are normally inferred from the ISA and ABI, but
1339           these flags force a certain group of registers to be treated as 64
1340           bits wide at all times.  -mgp64 controls the size of general-
1341           purpose registers and -mfp64 controls the size of floating-point
1342           registers.
1343
1344       -mfpxx
1345           The register sizes are normally inferred from the ISA and ABI, but
1346           using this flag in combination with -mabi=32 enables an ABI variant
1347           which will operate correctly with floating-point registers which
1348           are 32 or 64 bits wide.
1349
1350       -modd-spreg
1351       -mno-odd-spreg
1352           Enable use of floating-point operations on odd-numbered single-
1353           precision registers when supported by the ISA.  -mfpxx implies
1354           -mno-odd-spreg, otherwise the default is -modd-spreg.
1355
1356       -mips16
1357       -no-mips16
1358           Generate code for the MIPS 16 processor.  This is equivalent to
1359           putting ".module mips16" at the start of the assembly file.
1360           -no-mips16 turns off this option.
1361
1362       -mmips16e2
1363       -mno-mips16e2
1364           Enable the use of MIPS16e2 instructions in MIPS16 mode.  This is
1365           equivalent to putting ".module mips16e2" at the start of the
1366           assembly file.  -mno-mips16e2 turns off this option.
1367
1368       -mmicromips
1369       -mno-micromips
1370           Generate code for the microMIPS processor.  This is equivalent to
1371           putting ".module micromips" at the start of the assembly file.
1372           -mno-micromips turns off this option.  This is equivalent to
1373           putting ".module nomicromips" at the start of the assembly file.
1374
1375       -msmartmips
1376       -mno-smartmips
1377           Enables the SmartMIPS extension to the MIPS32 instruction set.
1378           This is equivalent to putting ".module smartmips" at the start of
1379           the assembly file.  -mno-smartmips turns off this option.
1380
1381       -mips3d
1382       -no-mips3d
1383           Generate code for the MIPS-3D Application Specific Extension.  This
1384           tells the assembler to accept MIPS-3D instructions.  -no-mips3d
1385           turns off this option.
1386
1387       -mdmx
1388       -no-mdmx
1389           Generate code for the MDMX Application Specific Extension.  This
1390           tells the assembler to accept MDMX instructions.  -no-mdmx turns
1391           off this option.
1392
1393       -mdsp
1394       -mno-dsp
1395           Generate code for the DSP Release 1 Application Specific Extension.
1396           This tells the assembler to accept DSP Release 1 instructions.
1397           -mno-dsp turns off this option.
1398
1399       -mdspr2
1400       -mno-dspr2
1401           Generate code for the DSP Release 2 Application Specific Extension.
1402           This option implies -mdsp.  This tells the assembler to accept DSP
1403           Release 2 instructions.  -mno-dspr2 turns off this option.
1404
1405       -mdspr3
1406       -mno-dspr3
1407           Generate code for the DSP Release 3 Application Specific Extension.
1408           This option implies -mdsp and -mdspr2.  This tells the assembler to
1409           accept DSP Release 3 instructions.  -mno-dspr3 turns off this
1410           option.
1411
1412       -mmsa
1413       -mno-msa
1414           Generate code for the MIPS SIMD Architecture Extension.  This tells
1415           the assembler to accept MSA instructions.  -mno-msa turns off this
1416           option.
1417
1418       -mxpa
1419       -mno-xpa
1420           Generate code for the MIPS eXtended Physical Address (XPA)
1421           Extension.  This tells the assembler to accept XPA instructions.
1422           -mno-xpa turns off this option.
1423
1424       -mmt
1425       -mno-mt
1426           Generate code for the MT Application Specific Extension.  This
1427           tells the assembler to accept MT instructions.  -mno-mt turns off
1428           this option.
1429
1430       -mmcu
1431       -mno-mcu
1432           Generate code for the MCU Application Specific Extension.  This
1433           tells the assembler to accept MCU instructions.  -mno-mcu turns off
1434           this option.
1435
1436       -mcrc
1437       -mno-crc
1438           Generate code for the MIPS cyclic redundancy check (CRC)
1439           Application Specific Extension.  This tells the assembler to accept
1440           CRC instructions.  -mno-crc turns off this option.
1441
1442       -mginv
1443       -mno-ginv
1444           Generate code for the Global INValidate (GINV) Application Specific
1445           Extension.  This tells the assembler to accept GINV instructions.
1446           -mno-ginv turns off this option.
1447
1448       -mloongson-mmi
1449       -mno-loongson-mmi
1450           Generate code for the Loongson MultiMedia extensions Instructions
1451           (MMI) Application Specific Extension.  This tells the assembler to
1452           accept MMI instructions.  -mno-loongson-mmi turns off this option.
1453
1454       -mloongson-cam
1455       -mno-loongson-cam
1456           Generate code for the Loongson Content Address Memory (CAM)
1457           instructions.  This tells the assembler to accept Loongson CAM
1458           instructions.  -mno-loongson-cam turns off this option.
1459
1460       -mloongson-ext
1461       -mno-loongson-ext
1462           Generate code for the Loongson EXTensions (EXT) instructions.  This
1463           tells the assembler to accept Loongson EXT instructions.
1464           -mno-loongson-ext turns off this option.
1465
1466       -mloongson-ext2
1467       -mno-loongson-ext2
1468           Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1469           This option implies -mloongson-ext.  This tells the assembler to
1470           accept Loongson EXT2 instructions.  -mno-loongson-ext2 turns off
1471           this option.
1472
1473       -minsn32
1474       -mno-insn32
1475           Only use 32-bit instruction encodings when generating code for the
1476           microMIPS processor.  This option inhibits the use of any 16-bit
1477           instructions.  This is equivalent to putting ".set insn32" at the
1478           start of the assembly file.  -mno-insn32 turns off this option.
1479           This is equivalent to putting ".set noinsn32" at the start of the
1480           assembly file.  By default -mno-insn32 is selected, allowing all
1481           instructions to be used.
1482
1483       --construct-floats
1484       --no-construct-floats
1485           The --no-construct-floats option disables the construction of
1486           double width floating point constants by loading the two halves of
1487           the value into the two single width floating point registers that
1488           make up the double width register.  By default --construct-floats
1489           is selected, allowing construction of these floating point
1490           constants.
1491
1492       --relax-branch
1493       --no-relax-branch
1494           The --relax-branch option enables the relaxation of out-of-range
1495           branches.  By default --no-relax-branch is selected, causing any
1496           out-of-range branches to produce an error.
1497
1498       -mignore-branch-isa
1499       -mno-ignore-branch-isa
1500           Ignore branch checks for invalid transitions between ISA modes.
1501           The semantics of branches does not provide for an ISA mode switch,
1502           so in most cases the ISA mode a branch has been encoded for has to
1503           be the same as the ISA mode of the branch's target label.
1504           Therefore GAS has checks implemented that verify in branch assembly
1505           that the two ISA modes match.  -mignore-branch-isa disables these
1506           checks.  By default -mno-ignore-branch-isa is selected, causing any
1507           invalid branch requiring a transition between ISA modes to produce
1508           an error.
1509
1510       -mnan=encoding
1511           Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1512           (-mnan=legacy) NaN encoding format.  The latter is the default.
1513
1514       --emulation=name
1515           This option was formerly used to switch between ELF and ECOFF
1516           output on targets like IRIX 5 that supported both.  MIPS ECOFF
1517           support was removed in GAS 2.24, so the option now serves little
1518           purpose.  It is retained for backwards compatibility.
1519
1520           The available configuration names are: mipself, mipslelf and
1521           mipsbelf.  Choosing mipself now has no effect, since the output is
1522           always ELF.  mipslelf and mipsbelf select little- and big-endian
1523           output respectively, but -EL and -EB are now the preferred options
1524           instead.
1525
1526       -nocpp
1527           as ignores this option.  It is accepted for compatibility with the
1528           native tools.
1529
1530       --trap
1531       --no-trap
1532       --break
1533       --no-break
1534           Control how to deal with multiplication overflow and division by
1535           zero.  --trap or --no-break (which are synonyms) take a trap
1536           exception (and only work for Instruction Set Architecture level 2
1537           and higher); --break or --no-trap (also synonyms, and the default)
1538           take a break exception.
1539
1540       -n  When this option is used, as will issue a warning every time it
1541           generates a nop instruction from a macro.
1542
1543       The following options are available when as is configured for a Meta
1544       processor.
1545
1546       "-mcpu=metac11"
1547           Generate code for Meta 1.1.
1548
1549       "-mcpu=metac12"
1550           Generate code for Meta 1.2.
1551
1552       "-mcpu=metac21"
1553           Generate code for Meta 2.1.
1554
1555       "-mfpu=metac21"
1556           Allow code to use FPU hardware of Meta 2.1.
1557
1558       See the info pages for documentation of the MMIX-specific options.
1559
1560       The following options are available when as is configured for a NDS32
1561       processor.
1562
1563       "-O1"
1564           Optimize for performance.
1565
1566       "-Os"
1567           Optimize for space.
1568
1569       "-EL"
1570           Produce little endian data output.
1571
1572       "-EB"
1573           Produce little endian data output.
1574
1575       "-mpic"
1576           Generate PIC.
1577
1578       "-mno-fp-as-gp-relax"
1579           Suppress fp-as-gp relaxation for this file.
1580
1581       "-mb2bb-relax"
1582           Back-to-back branch optimization.
1583
1584       "-mno-all-relax"
1585           Suppress all relaxation for this file.
1586
1587       "-march=<arch name>"
1588           Assemble for architecture <arch name> which could be v3, v3j, v3m,
1589           v3f, v3s, v2, v2j, v2f, v2s.
1590
1591       "-mbaseline=<baseline>"
1592           Assemble for baseline <baseline> which could be v2, v3, v3m.
1593
1594       "-mfpu-freg=FREG"
1595           Specify a FPU configuration.
1596
1597           "0      8 SP /  4 DP registers"
1598           "1     16 SP /  8 DP registers"
1599           "2     32 SP / 16 DP registers"
1600           "3     32 SP / 32 DP registers"
1601       "-mabi=abi"
1602           Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1603
1604       "-m[no-]mac"
1605           Enable/Disable Multiply instructions support.
1606
1607       "-m[no-]div"
1608           Enable/Disable Divide instructions support.
1609
1610       "-m[no-]16bit-ext"
1611           Enable/Disable 16-bit extension
1612
1613       "-m[no-]dx-regs"
1614           Enable/Disable d0/d1 registers
1615
1616       "-m[no-]perf-ext"
1617           Enable/Disable Performance extension
1618
1619       "-m[no-]perf2-ext"
1620           Enable/Disable Performance extension 2
1621
1622       "-m[no-]string-ext"
1623           Enable/Disable String extension
1624
1625       "-m[no-]reduced-regs"
1626           Enable/Disable Reduced Register configuration (GPR16) option
1627
1628       "-m[no-]audio-isa-ext"
1629           Enable/Disable AUDIO ISA extension
1630
1631       "-m[no-]fpu-sp-ext"
1632           Enable/Disable FPU SP extension
1633
1634       "-m[no-]fpu-dp-ext"
1635           Enable/Disable FPU DP extension
1636
1637       "-m[no-]fpu-fma"
1638           Enable/Disable FPU fused-multiply-add instructions
1639
1640       "-mall-ext"
1641           Turn on all extensions and instructions support
1642
1643       The following options are available when as is configured for a PowerPC
1644       processor.
1645
1646       -a32
1647           Generate ELF32 or XCOFF32.
1648
1649       -a64
1650           Generate ELF64 or XCOFF64.
1651
1652       -K PIC
1653           Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1654
1655       -mpwrx | -mpwr2
1656           Generate code for POWER/2 (RIOS2).
1657
1658       -mpwr
1659           Generate code for POWER (RIOS1)
1660
1661       -m601
1662           Generate code for PowerPC 601.
1663
1664       -mppc, -mppc32, -m603, -m604
1665           Generate code for PowerPC 603/604.
1666
1667       -m403, -m405
1668           Generate code for PowerPC 403/405.
1669
1670       -m440
1671           Generate code for PowerPC 440.  BookE and some 405 instructions.
1672
1673       -m464
1674           Generate code for PowerPC 464.
1675
1676       -m476
1677           Generate code for PowerPC 476.
1678
1679       -m7400, -m7410, -m7450, -m7455
1680           Generate code for PowerPC 7400/7410/7450/7455.
1681
1682       -m750cl, -mgekko, -mbroadway
1683           Generate code for PowerPC 750CL/Gekko/Broadway.
1684
1685       -m821, -m850, -m860
1686           Generate code for PowerPC 821/850/860.
1687
1688       -mppc64, -m620
1689           Generate code for PowerPC 620/625/630.
1690
1691       -me500, -me500x2
1692           Generate code for Motorola e500 core complex.
1693
1694       -me500mc
1695           Generate code for Freescale e500mc core complex.
1696
1697       -me500mc64
1698           Generate code for Freescale e500mc64 core complex.
1699
1700       -me5500
1701           Generate code for Freescale e5500 core complex.
1702
1703       -me6500
1704           Generate code for Freescale e6500 core complex.
1705
1706       -mspe
1707           Generate code for Motorola SPE instructions.
1708
1709       -mspe2
1710           Generate code for Freescale SPE2 instructions.
1711
1712       -mtitan
1713           Generate code for AppliedMicro Titan core complex.
1714
1715       -mppc64bridge
1716           Generate code for PowerPC 64, including bridge insns.
1717
1718       -mbooke
1719           Generate code for 32-bit BookE.
1720
1721       -ma2
1722           Generate code for A2 architecture.
1723
1724       -me300
1725           Generate code for PowerPC e300 family.
1726
1727       -maltivec
1728           Generate code for processors with AltiVec instructions.
1729
1730       -mvle
1731           Generate code for Freescale PowerPC VLE instructions.
1732
1733       -mvsx
1734           Generate code for processors with Vector-Scalar (VSX) instructions.
1735
1736       -mhtm
1737           Generate code for processors with Hardware Transactional Memory
1738           instructions.
1739
1740       -mpower4, -mpwr4
1741           Generate code for Power4 architecture.
1742
1743       -mpower5, -mpwr5, -mpwr5x
1744           Generate code for Power5 architecture.
1745
1746       -mpower6, -mpwr6
1747           Generate code for Power6 architecture.
1748
1749       -mpower7, -mpwr7
1750           Generate code for Power7 architecture.
1751
1752       -mpower8, -mpwr8
1753           Generate code for Power8 architecture.
1754
1755       -mpower9, -mpwr9
1756           Generate code for Power9 architecture.
1757
1758       -mcell
1759       -mcell
1760           Generate code for Cell Broadband Engine architecture.
1761
1762       -mcom
1763           Generate code Power/PowerPC common instructions.
1764
1765       -many
1766           Generate code for any architecture (PWR/PWRX/PPC).
1767
1768       -mregnames
1769           Allow symbolic names for registers.
1770
1771       -mno-regnames
1772           Do not allow symbolic names for registers.
1773
1774       -mrelocatable
1775           Support for GCC's -mrelocatable option.
1776
1777       -mrelocatable-lib
1778           Support for GCC's -mrelocatable-lib option.
1779
1780       -memb
1781           Set PPC_EMB bit in ELF flags.
1782
1783       -mlittle, -mlittle-endian, -le
1784           Generate code for a little endian machine.
1785
1786       -mbig, -mbig-endian, -be
1787           Generate code for a big endian machine.
1788
1789       -msolaris
1790           Generate code for Solaris.
1791
1792       -mno-solaris
1793           Do not generate code for Solaris.
1794
1795       -nops=count
1796           If an alignment directive inserts more than count nops, put a
1797           branch at the beginning to skip execution of the nops.
1798
1799       The following options are available when as is configured for a RISC-V
1800       processor.
1801
1802       -fpic
1803       -fPIC
1804           Generate position-independent code
1805
1806       -fno-pic
1807           Don't generate position-independent code (default)
1808
1809       -march=ISA
1810           Select the base isa, as specified by ISA.  For example
1811           -march=rv32ima.
1812
1813       -mabi=ABI
1814           Selects the ABI, which is either "ilp32" or "lp64", optionally
1815           followed by "f", "d", or "q" to indicate single-precision, double-
1816           precision, or quad-precision floating-point calling convention, or
1817           none to indicate the soft-float calling convention.  Also, "ilp32"
1818           can optionally be followed by "e" to indicate the RVE ABI, which is
1819           always soft-float.
1820
1821       -mrelax
1822           Take advantage of linker relaxations to reduce the number of
1823           instructions required to materialize symbol addresses. (default)
1824
1825       -mno-relax
1826           Don't do linker relaxations.
1827
1828       See the info pages for documentation of the RX-specific options.
1829
1830       The following options are available when as is configured for the s390
1831       processor family.
1832
1833       -m31
1834       -m64
1835           Select the word size, either 31/32 bits or 64 bits.
1836
1837       -mesa
1838       -mzarch
1839           Select the architecture mode, either the Enterprise System
1840           Architecture (esa) or the z/Architecture mode (zarch).
1841
1842       -march=processor
1843           Specify which s390 processor variant is the target, g5 (or arch3),
1844           g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
1845           (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), or
1846           z14 (or arch12).
1847
1848       -mregnames
1849       -mno-regnames
1850           Allow or disallow symbolic names for registers.
1851
1852       -mwarn-areg-zero
1853           Warn whenever the operand for a base or index register has been
1854           specified but evaluates to zero.
1855
1856       The following options are available when as is configured for a
1857       TMS320C6000 processor.
1858
1859       -march=arch
1860           Enable (only) instructions from architecture arch.  By default, all
1861           instructions are permitted.
1862
1863           The following values of arch are accepted: "c62x", "c64x", "c64x+",
1864           "c67x", "c67x+", "c674x".
1865
1866       -mdsbt
1867       -mno-dsbt
1868           The -mdsbt option causes the assembler to generate the
1869           "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1870           code is using DSBT addressing.  The -mno-dsbt option, the default,
1871           causes the tag to have a value of 0, indicating that the code does
1872           not use DSBT addressing.  The linker will emit a warning if objects
1873           of different type (DSBT and non-DSBT) are linked together.
1874
1875       -mpid=no
1876       -mpid=near
1877       -mpid=far
1878           The -mpid= option causes the assembler to generate the
1879           "Tag_ABI_PID" attribute with a value indicating the form of data
1880           addressing used by the code.  -mpid=no, the default, indicates
1881           position-dependent data addressing, -mpid=near indicates position-
1882           independent addressing with GOT accesses using near DP addressing,
1883           and -mpid=far indicates position-independent addressing with GOT
1884           accesses using far DP addressing.  The linker will emit a warning
1885           if objects built with different settings of this option are linked
1886           together.
1887
1888       -mpic
1889       -mno-pic
1890           The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1891           attribute with a value of 1, indicating that the code is using
1892           position-independent code addressing,  The "-mno-pic" option, the
1893           default, causes the tag to have a value of 0, indicating position-
1894           dependent code addressing.  The linker will emit a warning if
1895           objects of different type (position-dependent and position-
1896           independent) are linked together.
1897
1898       -mbig-endian
1899       -mlittle-endian
1900           Generate code for the specified endianness.  The default is little-
1901           endian.
1902
1903       The following options are available when as is configured for a TILE-Gx
1904       processor.
1905
1906       -m32 | -m64
1907           Select the word size, either 32 bits or 64 bits.
1908
1909       -EB | -EL
1910           Select the endianness, either big-endian (-EB) or little-endian
1911           (-EL).
1912
1913       The following option is available when as is configured for a Visium
1914       processor.
1915
1916       -mtune=arch
1917           This option specifies the target architecture.  If an attempt is
1918           made to assemble an instruction that will not execute on the target
1919           architecture, the assembler will issue an error message.
1920
1921           The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
1922
1923       The following options are available when as is configured for an Xtensa
1924       processor.
1925
1926       --text-section-literals | --no-text-section-literals
1927           Control the treatment of literal pools.  The default is
1928           --no-text-section-literals, which places literals in separate
1929           sections in the output file.  This allows the literal pool to be
1930           placed in a data RAM/ROM.  With --text-section-literals, the
1931           literals are interspersed in the text section in order to keep them
1932           as close as possible to their references.  This may be necessary
1933           for large assembly files, where the literals would otherwise be out
1934           of range of the "L32R" instructions in the text section.  Literals
1935           are grouped into pools following ".literal_position" directives or
1936           preceding "ENTRY" instructions.  These options only affect literals
1937           referenced via PC-relative "L32R" instructions; literals for
1938           absolute mode "L32R" instructions are handled separately.
1939
1940       --auto-litpools | --no-auto-litpools
1941           Control the treatment of literal pools.  The default is
1942           --no-auto-litpools, which in the absence of --text-section-literals
1943           places literals in separate sections in the output file.  This
1944           allows the literal pool to be placed in a data RAM/ROM.  With
1945           --auto-litpools, the literals are interspersed in the text section
1946           in order to keep them as close as possible to their references,
1947           explicit ".literal_position" directives are not required.  This may
1948           be necessary for very large functions, where single literal pool at
1949           the beginning of the function may not be reachable by "L32R"
1950           instructions at the end.  These options only affect literals
1951           referenced via PC-relative "L32R" instructions; literals for
1952           absolute mode "L32R" instructions are handled separately.  When
1953           used together with --text-section-literals, --auto-litpools takes
1954           precedence.
1955
1956       --absolute-literals | --no-absolute-literals
1957           Indicate to the assembler whether "L32R" instructions use absolute
1958           or PC-relative addressing.  If the processor includes the absolute
1959           addressing option, the default is to use absolute "L32R"
1960           relocations.  Otherwise, only the PC-relative "L32R" relocations
1961           can be used.
1962
1963       --target-align | --no-target-align
1964           Enable or disable automatic alignment to reduce branch penalties at
1965           some expense in code size.    This optimization is enabled by
1966           default.  Note that the assembler will always align instructions
1967           like "LOOP" that have fixed alignment requirements.
1968
1969       --longcalls | --no-longcalls
1970           Enable or disable transformation of call instructions to allow
1971           calls across a greater range of addresses.    This option should be
1972           used when call targets can potentially be out of range.  It may
1973           degrade both code size and performance, but the linker can
1974           generally optimize away the unnecessary overhead when a call ends
1975           up within range.  The default is --no-longcalls.
1976
1977       --transform | --no-transform
1978           Enable or disable all assembler transformations of Xtensa
1979           instructions, including both relaxation and optimization.  The
1980           default is --transform; --no-transform should only be used in the
1981           rare cases when the instructions must be exactly as specified in
1982           the assembly source.  Using --no-transform causes out of range
1983           instruction operands to be errors.
1984
1985       --rename-section oldname=newname
1986           Rename the oldname section to newname.  This option can be used
1987           multiple times to rename multiple sections.
1988
1989       --trampolines | --no-trampolines
1990           Enable or disable transformation of jump instructions to allow
1991           jumps across a greater range of addresses.    This option should be
1992           used when jump targets can potentially be out of range.  In the
1993           absence of such jumps this option does not affect code size or
1994           performance.  The default is --trampolines.
1995
1996       The following options are available when as is configured for a Z80
1997       family processor.
1998
1999       -z80
2000           Assemble for Z80 processor.
2001
2002       -r800
2003           Assemble for R800 processor.
2004
2005       -ignore-undocumented-instructions
2006       -Wnud
2007           Assemble undocumented Z80 instructions that also work on R800
2008           without warning.
2009
2010       -ignore-unportable-instructions
2011       -Wnup
2012           Assemble all undocumented Z80 instructions without warning.
2013
2014       -warn-undocumented-instructions
2015       -Wud
2016           Issue a warning for undocumented Z80 instructions that also work on
2017           R800.
2018
2019       -warn-unportable-instructions
2020       -Wup
2021           Issue a warning for undocumented Z80 instructions that do not work
2022           on R800.
2023
2024       -forbid-undocumented-instructions
2025       -Fud
2026           Treat all undocumented instructions as errors.
2027
2028       -forbid-unportable-instructions
2029       -Fup
2030           Treat undocumented Z80 instructions that do not work on R800 as
2031           errors.
2032

SEE ALSO

2034       gcc(1), ld(1), and the Info entries for binutils and ld.
2035
2037       Copyright (c) 1991-2019 Free Software Foundation, Inc.
2038
2039       Permission is granted to copy, distribute and/or modify this document
2040       under the terms of the GNU Free Documentation License, Version 1.3 or
2041       any later version published by the Free Software Foundation; with no
2042       Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2043       Texts.  A copy of the license is included in the section entitled "GNU
2044       Free Documentation License".
2045
2046
2047
2048binutils-2.32                     2019-02-02                             AS(1)
Impressum