vhier(1) - f32

1VHIER(1)              User Contributed Perl Documentation             VHIER(1)
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NAME

6       vhier - Return all files in a verilog hierarchy using Verilog::Netlist
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SYNOPSIS

9         vhier --help
10         vhier [verilog_options] [-o filename] [verilog_files.v...]
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DESCRIPTION

13       Vhier reads the Verilog files passed on the command line and outputs a
14       tree of all of the filenames, modules, and cells referenced by that
15       file.
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VERILOG ARGUMENTS

18       The following arguments are compatible with GCC, VCS and most Verilog
19       programs.
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21       +define+var+value =item -Dvar=value
22           Defines the given preprocessor symbol.
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24       -F file
25           Read the specified file, and act as if all text inside it was
26           specified as command line parameters.  Any relative paths are
27           relative to the directory containing the specified file.
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29       -f file
30           Read the specified file, and act as if all text inside it was
31           specified as command line parameters.  Any relative paths are
32           relative to the current directory.
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34       +incdir+dir =item -Idir
35           Add the directory to the list of directories that should be
36           searched for include directories or libraries.
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38       +libext+ext+ext...
39           Specify the extensions that should be used for finding modules.  If
40           for example module x is referenced, look in x.ext.
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42       -sv Specifies SystemVerilog language features should be enabled;
43           equivalent to "--language 1800-2017".  This option is selected by
44           default, it exists for compatibility with other simulators.
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46       -y dir
47           Add the directory to the list of directories that should be
48           searched for include directories or libraries.
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VHIER ARGUMENTS

51       --help
52           Displays this message and program version and exits.
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54       --o file
55           Use the given filename for output instead of stdout.
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57       --cells
58           Show the module name of all cells in top-down order.
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60       --forest
61           Show "ASCII-art" hierarchy tree of all cells (like ps --forest)
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63       --input-files
64           Show all input filenames.  Copying all of these files should result
65           in only those files needed to represent the entire design.
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67       --instance
68           With --cells or --forest, show module instance names.
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70       --language
71       <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>
72           Set the language standard for the files.  This determines which
73           tokens are signals versus keywords, such as the ever-common "do"
74           (data-out signal, versus a do-while loop keyword).
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76       --resolve-files
77           Show resolved filenames passed on the command line.  This will
78           convert raw module and filenames without paths to include the
79           library search path directory.  Output filenames will be in the
80           same order as passed on the command line.  Unlike --input-files or
81           --module-files, hierarchy is not traversed.
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83       --module-files
84           Show all module filenames in top-down order.  Child modules will
85           always appear as low as possible, so that reversing the list will
86           allow bottom-up processing of modules.  Unlike input-files, header
87           files are not included.
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89       --modules
90           Show all module names.
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92       --no-missing
93           Do not complain about references to missing modules.
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95       --missing-modules
96           With --nomissing, show all modules that are not found.
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98       --skiplist file
99           Given file contains a list of regular expressions, one per line. If
100           a module name in the design hierarchy matches one of these
101           expressions, skip showing that module and any sub-hierarchy.
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103       --synthesis
104           Define SYNTHESIS, and ignore text between "ambit", "pragma",
105           "synopsys" or "synthesis" translate_off and translate_on meta
106           comments.  Note using metacomments is discouraged as they have led
107           to silicon bugs (versus ifdef SYNTHESIS); see
108           <http://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf>.
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110       --top-module module
111           Start the report at the specified module name, ignoring all modules
112           that are not the one specified with --top-module or below, and
113           report an error if the --top-module specified does not exist.
114           Without this option vhier will report all modules, starting at the
115           module(s) that have no children below them.
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117           Note this option will not change the result of the --input-files
118           list, as the files needed to parse any design are independent of
119           which modules are used.
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121       --version
122           Displays program version and exits.
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124       --xml
125           Create output in XML format.
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DISTRIBUTION

128       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
129       software tool suite.  The latest version is available from CPAN and
130       from <http://www.veripool.org/verilog-perl>.
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132       Copyright 2005-2020 by Wilson Snyder.  This package is free software;
133       you can redistribute it and/or modify it under the terms of either the
134       GNU Lesser General Public License Version 3 or the Perl Artistic
135       License Version 2.0.
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AUTHORS

138       Wilson Snyder <wsnyder@wsnyder.org>
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