Verilog::Netlist::Port(3pm)

1Netlist::Port(3)      User Contributed Perl Documentation     Netlist::Port(3)
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NAME

6       Verilog::Netlist::Port - Port for a Verilog Module
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SYNOPSIS

9         use Verilog::Netlist;
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11         ...
12         my $port = $module->find_port('pinname');
13         print $port->name;
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DESCRIPTION

16       A Verilog::Netlist::Port object is created by Verilog::Netlist::Module
17       for every port connection in the module.
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ACCESSORS

20       See also Verilog::Netlist::Subclass for additional accessors and
21       methods.
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23       $self->array
24           Any array declaration for the port.  This only applies to Verilog
25           1995 style ports which can declare port bits independently from the
26           signal declarations.  When using Verilog 2001 style ports, see the
27           matching net declaration's data_type, msb and lsb methods instead,
28           for example "$module-"find_net($port->name)->data_type>.
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30       $self->comment
31           Returns any comments following the definition.  keep_comments=>1
32           must be passed to Verilog::Netlist::new for comments to be
33           retained.
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35       $self->data_type
36           The SystemVerilog data type of the port.
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38       $self->direction
39           The direction of the port: "in", "out", or "inout".
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41       $self->module
42           Reference to the Verilog::Netlist::Module the port is in.
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44       $self->name
45           The name of the port.
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47       $self->net
48           Reference to the Verilog::Netlist::Net the port connects to.  Only
49           valid after the netlist is linked.
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51       $self->type
52           Approximately an alias of data_type for backward compatibility.  Do
53           not use for new applications.
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MEMBER FUNCTIONS

56       See also Verilog::Netlist::Subclass for additional accessors and
57       methods.
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59       $self->dump
60           Prints debugging information for this port.
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DISTRIBUTION

63       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
64       EDA software tool suite.  The latest version is available from CPAN and
65       from <https://www.veripool.org/verilog-perl>.
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67       Copyright 2000-2020 by Wilson Snyder.  This package is free software;
68       you can redistribute it and/or modify it under the terms of either the
69       GNU Lesser General Public License Version 3 or the Perl Artistic
70       License Version 2.0.
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AUTHORS

73       Wilson Snyder <wsnyder@wsnyder.org>
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