1SigParser(3)          User Contributed Perl Documentation         SigParser(3)
2
3
4

NAME

6       Verilog::SigParser - Signal Parsing for Verilog language files
7

SYNOPSIS

9         use Verilog::Preproc;
10         use Verilog::SigParser;
11
12         my $pp = Verilog::Preproc->new(keep_comments=>0,);
13
14         my $parser = new Verilog::SigParser;
15         $parser->parse_preproc_file($pp);
16         # The below described callbacks are then invoked
17

DESCRIPTION

19       Verilog::SigParser builds upon the Verilog::Parser module to provide
20       callbacks for when a signal is declared, a module instantiated, or a
21       module defined.
22
23       See the "Which Package" section of Verilog::Language if you are unsure
24       which parsing package to use for a new application.  For a higher level
25       interface to this package, see Verilog::Netlist.
26

METHODS

28       The method interface to Verilog::SigParser is described in the
29       Verilog::Parser module which this package inherits.  You will probably
30       want to use the preprocessing option of Verilog::Parser with this
31       package.
32

CALLBACKS

34       In order to make the parser do anything interesting, you must make a
35       subclass where you override one or more of the following methods as
36       appropriate.
37
38       Note Verilog::Parser callbacks also are invoked when SigParser is
39       parsing.
40
41       $self->attribute($text)
42           Scanned an attribute or meta-comment.  The parser inspects the
43           first word of each comment line ("//key rest" to end of line) or
44           comment block ("/*key rest */).  It calls "$self-"attribute(
45           meta_text )" if the first word has a true value in hash
46           "$self-"metacomment>.
47
48       $self->class($token, $name, $virtual)
49           This method is called at a class.
50
51       $self->covergroup($token, $name)
52           This method is called at a covergroup.
53
54       $self->contassign($token, $lhs, $rhs)
55           This method is called at a continuous "assign" keyword, with the
56           left and right hand part of the assignment.  Note that "wire"
57           initializations are not considered assignments; those are received
58           via the var callback's value parameter.
59
60       $self->defparam($token, $lhs, $rhs)
61           This method is called at a "defparam" keyword, with the left and
62           right hand part of the assignment.
63
64       $self->endcell($token)
65           This method is called at the end of defining a cell. It is useful
66           for writing clean up routines.
67
68       $self->endgroup($token)
69           This method is called at the end of defining a covergroup. It is
70           useful for writing clean up routines.
71
72       $self->endinterface($token)
73           This method is called at a endinterface keyword. It is useful for
74           writing clean up routines.
75
76       $self->endclass($token)
77           This method is called at a endclass keyword.  It is useful for
78           writing clean up routines.
79
80       $self->endtaskfunc($token)
81           This method is called at a endfunction or endtask keyword.  It is
82           useful for writing clean up routines.
83
84       $self->endmodport($token)
85           This method is called at a endmodport keyword. It is useful for
86           writing clean up routines.
87
88       $self->endmodule($token)
89           This method is called at a endmodule keyword. It is useful for
90           writing clean up routines.
91
92       $self->endpackage($token)
93           This method is called at a endpackage keyword. It is useful for
94           writing clean up routines.
95
96       $self->endprogram($token)
97           This method is called at a endprogram keyword. It is useful for
98           writing clean up routines.
99
100       $self->function($keyword, $name, $data-type)
101           This method is called when a function is defined.  Type is the
102           output size or typename, plus "signed", for example "", "[3:0]",
103           "integer", or "signed [2:0]".
104
105       $self->import($package, $id)
106           This method is called when an import is defined.
107
108       $self->instant($module, $cell, $range)
109           This method is called when a instantiation is defined.  The first
110           parameter is the name of the module being instantiated. The second
111           parameter is the name of the cell, which may be "" for primitives.
112           The third is the range if the cell was arrayed.
113
114           Prior to version 3.000, the name of the parameters were also
115           included in this callback. This has been replaced with the parampin
116           callback.
117
118       $self->interface($keyword, $name)
119           This method is called when an interface is defined.
120
121       $self->modport($keyword, $name)
122           This method is called when an interface modport is defined.
123
124       $self->module($keyword, $name, ignored, $in_celldefine)
125           This method is called when a module is defined.
126
127       $self->package($keyword, $name)
128           This method is called when a package is defined.
129
130       $self->parampin($name, $connection, $index)
131           This method is called when a parameter is connected to an
132           instantiation, IE the "#(...)" syntax.  It is also used for UDP
133           delays (Three calls for "#(delay0,delay1,delay2)"), as the parser
134           does not know if the instantiation is for an UDP versus a module.
135
136       $self->pin($name, $connection, $index)
137           This method is called when a pin on an instant is defined and
138           "use_pinselects" is not set (the default, see pinselects() below.
139           If a pin name was not provided and the connection is by position,
140           name will be '' or undef.
141
142           If you do not need the pin nor var nor port callbacks, consider the
143           "$self->new (... use_vars=>0 ...)"  option to accelerate parsing.
144
145       $self->pinselects($name, $connections, $index)
146           If "$self->new (... use_pinselects=>1 ...)" is used this function
147           is called instead of "$self->pin (...)".  The difference is that
148           the second parameter ("$connections") is a Perl hash that contains
149           all connected nets in the case of concatenations including the MSB
150           and LSB bounds used at these locations.
151
152       $self->port($name, $objof, $direction, $data_type, $array, $pinnum)
153           This method is called when a module port is defined.  It may be
154           called twice on a port if the 1995 style is used; the first call is
155           made at the port header, the second call at the input/output
156           declaration.
157
158           The first argument $name, is the name of the port.  $objof is what
159           the port is an object of ('module', 'function', etc).  $direction
160           is the port direction ('input', 'output', 'inout', 'ref', 'const
161           ref', or 'interface').  $data_type is the data type ('reg',
162           'user_type_t', 'signed [31:0]', etc, or for interfaces the
163           "{interface_id}.{modport_name}").  $array is the arraying of the
164           port ('[1:0][2:0]', '', etc).  $pinnum is set to the pin number for
165           ANSI style declarations, and 0 for Verilog 1995 declarations made
166           outside the port list.
167
168           If you do not need the pin nor var nor port callbacks, consider the
169           "$self->new (... use_vars=>0 ...)"  option to accelerate parsing.
170
171       $self->program($keyword, $name)
172           This method is called when a program is defined.
173
174       $self->signal_decl($keyword, $signame, $vector, $mem, $signed, $value)
175           This method is no longer used, see $self->var.
176
177       $self->task($keyword, $name)
178           This method is called when a task is defined.
179
180       $self->var($kwd, $name, $objof, $nettype, $data_type, $array, $value)
181           This method is called when a variable or net is defined.
182
183           The first argument $kwd is how it was declared ('port', 'var',
184           'genvar', 'parameter', 'localparam', 'typedef') or if applicable a
185           net type ('supply0', 'wire', etc). $name is the name of the
186           variable.  $objof is what the variable is an object of ('module',
187           'function', etc).  $nettype is the net type if any was defined ('',
188           'supply0', 'wire', 'tri', etc).  $data_type is the data type
189           ('user_type_t', '[31:0] signed', etc).  $array is the arraying of
190           the variable which is the text AFTER the variable name
191           ('[1:0][2:0]', '', etc).  $value is what the variable was assigned
192           to ('', or expression).
193
194           Note typedefs are included here, because "parameter type" is both a
195           variable and a type declaration.
196
197           If you do not need the pin nor var nor port callbacks, consider the
198           "$self->new (... use_vars=>0 ...)"  option to accelerate parsing.
199
200           Below are some example declarations and the callbacks:
201
202              reg [4:0]  vect = 5'b10100;
203              # VAR  'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100'
204              wire (weak0, weak1) value = pullval;
205              # VAR  'net' 'value' 'module' 'wire' '' '' 'pullval'
206              reg [1:0] mem [12:2];
207              # VAR  'var' 'mem' 'module' '' 'reg [1:0]' '[12:2]' ''
208              int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
209              # verilog/parser_sv.v:121: VAR  'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}'
210              module ( output logic [SZ-1:0] o_sized );
211              # VAR  'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' ''
212              struct packed signed { bit [7:0] m_b; };
213              # VAR  'member' 'm_b' 'struct' '' 'bit [7:0]' '' ''
214

BUGS

216       This is being distributed as a baseline for future contributions.
217       Don't expect a lot, the Parser is still naive, and there are many
218       awkward cases that aren't covered.
219
220       Note the SigParser is focused on extracting signal information.  It
221       does NOT extract enough information to derive general interconnect; for
222       example the contents of 'assign' statements are not parsed.
223

DISTRIBUTION

225       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
226       EDA software tool suite.  The latest version is available from CPAN and
227       from <https://www.veripool.org/verilog-perl>.
228
229       Copyright 2000-2022 by Wilson Snyder.  This package is free software;
230       you can redistribute it and/or modify it under the terms of either the
231       GNU Lesser General Public License Version 3 or the Perl Artistic
232       License Version 2.0.
233

AUTHORS

235       Wilson Snyder <wsnyder@wsnyder.org>
236

SEE ALSO

238       Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist,
239       Verilog::Getopt
240
241
242
243perl v5.38.0                      2023-07-21                      SigParser(3)
Impressum