1Syntax::Highlight::EngiUnsee:r:KCaotnet:r:iVbeurtSieyldnotgPa(ex3r:)l:HDiogchulmiegnhtta:t:iEonngine::Kate::Verilog(3)
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NAME

6       Syntax::Highlight::Engine::Kate::Verilog - a Plugin for Verilog syntax
7       highlighting
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SYNOPSIS

10        require Syntax::Highlight::Engine::Kate::Verilog;
11        my $sh = new Syntax::Highlight::Engine::Kate::Verilog([
12        ]);
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DESCRIPTION

15       Syntax::Highlight::Engine::Kate::Verilog is a  plugin module that
16       provides syntax highlighting for Verilog to the
17       Syntax::Haghlight::Engine::Kate highlighting engine.
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19       This code is generated from the syntax definition files used by the
20       Kate project.  It works quite fine, but can use refinement and
21       optimization.
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23       It inherits Syntax::Higlight::Engine::Kate::Template. See also there.
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AUTHOR

26       Hans Jeuken (haje <at> toneel <dot> demon <dot> nl)
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BUGS

29       Unknown. If you find any, please contact the author
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33perl v5.10.1                      20S0y8n-t0a2x-:0:3Highlight::Engine::Kate::Verilog(3)
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