1LIBPFM(3) Linux Programmer's Manual LIBPFM(3)
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6 libpfm_intel_wsm - support for Intel Westmere core PMU
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9 #include <perfmon/pfmlib.h>
10 PMU name: wsm
12 PMU desc: Intel Westmere
13 PMU name: wsm_dp
14 PMU desc: Intel Westmere DP
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18 The library supports the Intel Westmere core PMU. It should be noted
19 that this PMU model only covers the each core's PMU and not the socket
20 level PMU. It is provided separately. Support is provided for the Intel
21 Core i7 and Core i5 processors (models 37, 44).
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25 The following modifiers are supported on Intel Westmere processors:
26 u Measure at user level which includes privilege levels 1, 2, 3.
28 This corresponds to PFM_PLM3. This is a boolean modifier.
29 k Measure at kernel level which includes privilege level 0. This
31 corresponds to PFM_PLM0. This is a boolean modifier.
32 i Invert the meaning of the event. The counter will now count
34 cycles in which the event is not occurring. This is a boolean
35 modifier
36 e Enable edge detection, i.e., count only when there is a state
38 transition from no occurrence of the event to at least one
39 occurrence. This modifier must be combined with a counter mask
40 modifier (m) with a value greater or equal to one. This is a
41 boolean modifier.
42 c Set the counter mask value. The mask acts as a threshold. The
44 counter will count the number of cycles in which the number of
45 occurrences of the event is greater or equal to the threshold.
46 This is an integer modifier with values in the range [0:255].
47 t Measure on both threads at the same time assuming hyper-thread‐
49 ing is enabled. This is a boolean modifier.
50 ldlat Pass a latency threshold to the
52 MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD event. This is an
53 integer attribute that must be in the range [3:65535]. It is
54 required for this event. Note that the event must be used with
55 precise sampling (PEBS).
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59 The library is able to encode the OFFCORE_RESPONSE_0 and OFF‐
60 CORE_RESPONSE_1 events. Those are special events because they, each,
61 need a second MSR (0x1a6 and 0x1a7 respectively) to be programmed for
62 the event to count properly. Thus two values are necessary for each
63 event. The first value can be programmed on any of the generic coun‐
64 ters. The second value goes into the dedicated MSR (0x1a6 or 0x1a7).
65 The OFFCORE_RESPONSE events are exposed as normal events with several
67 umasks which are divided in two groups: request and response. The user
68 must provide at least one umask from each group. For instance, OFF‐
69 CORE_RESPONSE_0:ANY_DATA:LOCAL_DRAM.
70 When using pfm_get_event_encoding(), two 64-bit values are returned.
72 The first value corresponds to what needs to be programmed into any of
73 the generic counters. The second value must be programmed into the cor‐
74 responding dedicated MSR (0x1a6 or 0x1a7).
75 When using an OS-specific encoding routine, the way the event is
77 encoded is OS specific. Refer to the corresponding man page for more
78 information.
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82 Stephane Eranian <eranian@gmail.com>
83 September, 2009 LIBPFM(3)