1STRUCT IRQ_CHIP_GENE(9) Structures STRUCT IRQ_CHIP_GENE(9)
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6 struct_irq_chip_generic - Generic irq chip data structure
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9 struct irq_chip_generic {
10 raw_spinlock_t lock;
11 void __iomem * reg_base;
12 unsigned int irq_base;
13 unsigned int irq_cnt;
14 u32 mask_cache;
15 u32 type_cache;
16 u32 polarity_cache;
17 u32 wake_enabled;
18 u32 wake_active;
19 unsigned int num_ct;
20 void * private;
21 struct list_head list;
22 struct irq_chip_type chip_types[0];
23 };
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26 lock
27 Lock to protect register and cache data access
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29 reg_base
30 Register base address (virtual)
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32 irq_base
33 Interrupt base nr for this chip
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35 irq_cnt
36 Number of interrupts handled by this chip
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38 mask_cache
39 Cached mask register
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41 type_cache
42 Cached type register
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44 polarity_cache
45 Cached polarity register
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47 wake_enabled
48 Interrupt can wakeup from suspend
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50 wake_active
51 Interrupt is marked as an wakeup from suspend source
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53 num_ct
54 Number of available irq_chip_type instances (usually 1)
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56 private
57 Private data for non generic chip callbacks
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59 list
60 List head for keeping track of instances
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62 chip_types[0]
63 Array of interrupt irq_chip_types
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66 Note, that irq_chip_generic can have multiple irq_chip_type
67 implementations which can be associated to a particular irq line of an
68 irq_chip_generic instance. That allows to share and protect state in an
69 irq_chip_generic instance when we need to implement different flow
70 mechanisms (level/edge) for it.
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73 Thomas Gleixner <tglx@linutronix.de>
74 Author.
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76 Ingo Molnar <mingo@elte.hu>
77 Author.
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80Kernel Hackers Manual 3.10 June 2019 STRUCT IRQ_CHIP_GENE(9)