1STRUCT SPI_MASTER(9) Serial Peripheral Interface (S STRUCT SPI_MASTER(9)
2
6 struct_spi_master - interface to SPI master controller
7
9 struct spi_master {
10 struct device dev;
11 struct list_head list;
12 s16 bus_num;
13 u16 num_chipselect;
14 u16 dma_alignment;
15 u16 mode_bits;
16 u32 bits_per_word_mask;
17 u16 flags;
18 #define SPI_MASTER_HALF_DUPLEX BIT(0)
19 #define SPI_MASTER_NO_RX BIT(1)
20 #define SPI_MASTER_NO_TX BIT(2)
21 spinlock_t bus_lock_spinlock;
22 struct mutex bus_lock_mutex;
23 bool bus_lock_flag;
24 int (* setup) (struct spi_device *spi);
25 int (* transfer) (struct spi_device *spi,struct spi_message *mesg);
26 void (* cleanup) (struct spi_device *spi);
27 bool queued;
28 struct kthread_worker kworker;
29 struct task_struct * kworker_task;
30 struct kthread_work pump_messages;
31 spinlock_t queue_lock;
32 struct list_head queue;
33 struct spi_message * cur_msg;
34 bool busy;
35 bool running;
36 bool rt;
37 int (* prepare_transfer_hardware) (struct spi_master *master);
38 int (* transfer_one_message) (struct spi_master *master,struct spi_message *mesg);
39 int (* unprepare_transfer_hardware) (struct spi_master *master);
40 int * cs_gpios;
41 };
42
44 dev
45 device interface to this driver
46 list
48 link with the global spi_master list
49 bus_num
51 board-specific (and often SOC-specific) identifier for a given SPI
52 controller.
53 num_chipselect
55 chipselects are used to distinguish individual SPI slaves, and are
56 numbered from zero to num_chipselects. each slave has a chipselect
57 signal, but it's common that not every chipselect is connected to a
58 slave.
59 dma_alignment
61 SPI controller constraint on DMA buffers alignment.
62 mode_bits
64 flags understood by this controller driver
65 bits_per_word_mask
67 A mask indicating which values of bits_per_word are supported by
68 the driver. Bit n indicates that a bits_per_word n+1 is suported.
69 If set, the SPI core will reject any transfer with an unsupported
70 bits_per_word. If not set, this value is simply ignored, and it's
71 up to the individual driver to perform any validation.
72 flags
74 other constraints relevant to this driver
75 bus_lock_spinlock
77 spinlock for SPI bus locking
78 bus_lock_mutex
80 mutex for SPI bus locking
81 bus_lock_flag
83 indicates that the SPI bus is locked for exclusive use
84 setup
86 updates the device mode and clocking records used by a device's SPI
87 controller; protocol code may call this. This must fail if an
88 unrecognized or unsupported mode is requested. It's always safe to
89 call this unless transfers are pending on the device whose settings
90 are being modified.
91 transfer
93 adds a message to the controller's transfer queue.
94 cleanup
96 frees controller-specific state
97 queued
99 whether this master is providing an internal message queue
100 kworker
102 thread struct for message pump
103 kworker_task
105 pointer to task for message pump kworker thread
106 pump_messages
108 work struct for scheduling work to the message pump
109 queue_lock
111 spinlock to syncronise access to message queue
112 queue
114 message queue
115 cur_msg
117 the currently in-flight message
118 busy
120 message pump is busy
121 running
123 message pump is running
124 rt
126 whether this queue is set to run as a realtime task
127 prepare_transfer_hardware
129 a message will soon arrive from the queue so the subsystem requests
130 the driver to prepare the transfer hardware by issuing this call
131 transfer_one_message
133 the subsystem calls the driver to transfer a single message while
134 queuing transfers that arrive in the meantime. When the driver is
135 finished with this message, it must call
136 spi_finalize_current_message so the subsystem can issue the next
137 transfer
138 unprepare_transfer_hardware
140 there are currently no more messages on the queue so the subsystem
141 notifies the driver that it may relax the hardware by issuing this
142 call
143 cs_gpios
145 Array of GPIOs to use as chip select lines; one per CS number. Any
146 individual value may be -ENOENT for CS lines that are not GPIOs
147 (driven by the SPI controller itself).
148
150 Each SPI master controller can communicate with one or more spi_device
151 children. These make a small bus, sharing MOSI, MISO and SCK signals
152 but not chip select signals. Each device may be configured to use a
153 different clock rate, since those shared signals are ignored unless the
154 chip is selected.
155 The driver for an SPI controller manages access to those devices
157 through a queue of spi_message transactions, copying data between CPU
158 memory and an SPI slave device. For each such message it queues, it
159 calls the message's completion function when the transaction completes.
160
162Kernel Hackers Manual 3.10 June 2019 STRUCT SPI_MASTER(9)