sp_preproc(1)

1SP_PREPROC(1)         User Contributed Perl Documentation        SP_PREPROC(1)
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NAME

6       sp_preproc - SystemPerl Preprocessor
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SYNOPSIS

9         sp_preproc <file.sp>
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DESCRIPTION

12       sp_preproc takes a .sp (systemperl) file and creates the SystemC header
13       and C files.
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15       It is generally only executed from the standard build scripts.
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ARGUMENTS

18       --help
19           Displays this message and program version and exits.
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21       --hier-only
22           Read only hierarchy information, ignore all signal information.
23           Useful for faster generation of sp_lib files.
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25       --inline
26           Edit the existing source code "inline".  Similar to the Verilog-
27           mode AUTOs.  Use --inline --noautos to remove the expanded
28           automatics.
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30       --libfile filename
31           Filename to write a list of sp_cells into, for later use as a
32           --libcell to another sp_preproc run.
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34       --libfile-libcells
35           Include library cells in the --libfile report.
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37       --libcell
38           Files listed before --libcell will be preprocessed or inlined as
39           appropriate.  Files after noexpand will only be used for resolving
40           references, they will not be linked, linted, or otherwise checked.
41           --nolibcell can be used to re-enable checking of subsequent files.
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43       --M filename
44       --MMD filename
45           Write dependencies in Makefile format to the specified filename.
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47       --Mdir dirname
48           Write preprocessor outputs to the specified directory instead of
49           the current directory.
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51       --ncsc
52           Create output files compatible with Cadence NC-SystemC.
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54       --nolint
55           Disable lint style error checks, such as required to run doxygen on
56           the SystemPerl output.
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58       --preproc
59           Preprocess the code, writing to separate header and cpp files.
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61       --trace-duplicates
62           Include code to trace submodule signals connected directly to a
63           parent signal, generally for debugging interconnect.  Without this
64           switch such signals will be presumed to have the value of their
65           parent module's signal, speeding and compressing traces.
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67       --tree filename
68           Write a report showing the design hierarchy tree to the specified
69           filename.  This format may change, it should not be parsed by
70           tools.
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72       --noautos
73           With --inline, remove any expanded automatics.
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75       --verbose
76           Shows which files are being written, or are the same.
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78       --version
79           Displays program version and exits.
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81       --write-verilog filename
82           Write the SystemC interconnections in Verilog format to the
83           specified filename.  Note this does not include logic, it only
84           contains module ports and cells.
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86       -M filename
87           Writes the dependency listing (similar to cpp -M) to the specified
88           filename.
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90       -Dvar=value
91           Sets a define to the given value (similar to cpp -D).
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93       -f file
94           Parse parameters from the given file.
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LANGUAGE

97       See SystemC::SystemPerl for the language specification.
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DISTRIBUTION

100       SystemPerl is part of the <http://www.veripool.org/> free SystemC
101       software tool suite.  The latest version is available from CPAN and
102       from <http://www.veripool.org/systemperl>.
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104       Copyright 2001-2010 by Wilson Snyder.  This package is free software;
105       you can redistribute it and/or modify it under the terms of either the
106       GNU Lesser General Public License Version 3 or the Perl Artistic
107       License Version 2.0.
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AUTHORS

110       Wilson Snyder <wsnyder@wsnyder.org>
111