1Netlist::ContAssign(3)User Contributed Perl DocumentationNetlist::ContAssign(3)
2
3
4

NAME

6       Verilog::Netlist::ContAssign - ContAssign assignment
7

SYNOPSIS

9         use Verilog::Netlist;
10
11         ...
12         foreach my $cont ($module->statements)
13           print $cont->name;
14

DESCRIPTION

16       A Verilog::Netlist::ContAssign object is created by Verilog::Netlist
17       for every continuous assignment statement in the current module.
18

ACCESSORS

20       See also Verilog::Netlist::Subclass for additional accessors and
21       methods.
22
23       $self->keyword
24           Keyword used to declare the assignment.  Currently "assign" is the
25           only supported value.
26
27       $self->lhs
28           Left hand side of the assignment.
29
30       $self->module
31           Pointer to the module the cell is in.
32
33       $self->netlist
34           Reference to the Verilog::Netlist the cell is under.
35
36       $self->rhs
37           Right hand side of the assignment.
38

MEMBER FUNCTIONS

40       See also Verilog::Netlist::Subclass for additional accessors and
41       methods.
42
43       $self->dump
44           Prints debugging information for this cell.
45

DISTRIBUTION

47       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
48       software tool suite.  The latest version is available from CPAN and
49       from http://www.veripool.org/verilog-perl
50       <http://www.veripool.org/verilog-perl>.
51
52       Copyright 2000-2010 by Wilson Snyder.  This package is free software;
53       you can redistribute it and/or modify it under the terms of either the
54       GNU Lesser General Public License Version 3 or the Perl Artistic
55       License Version 2.0.
56

AUTHORS

58       Wilson Snyder <wsnyder@wsnyder.org>
59

SEE ALSO

61       Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist
62
63
64
65perl v5.12.2                      2010-10-25            Netlist::ContAssign(3)
Impressum