perl-Verilog-Perl/vhier(1)

1VHIER(1)              User Contributed Perl Documentation             VHIER(1)
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NAME

6       vhier - Return all files in a verilog hierarchy using Verilog::Netlist
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SYNOPSIS

9         vhier --help
10         vhier [verilog_options] [-o filename] [verilog_files.v...]
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DESCRIPTION

13       Vhier reads the Verilog files passed on the command line and outputs a
14       tree of all of the filenames, modules, and cells referenced by that
15       file.
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VERILOG ARGUMENTS

18       The following arguments are compatible with GCC, VCS and most Verilog
19       programs.
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21       +define+var+value =item -Dvar=value
22           Defines the given preprocessor symbol.
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24       -f file
25           Read the specified file, and act as if all text inside it was
26           specified as command line parameters.
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28       +incdir+dir =item -Idir
29           Add the directory to the list of directories that should be
30           searched for include directories or libraries.
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32       +libext+ext+ext...
33           Specify the extensions that should be used for finding modules.  If
34           for example module x is referenced, look in x.ext.
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36       -sv Specifies SystemVerilog language features should be enabled;
37           equivalent to "--language 1800-2009".  This option is selected by
38           default, it exists for compatibility with other simulators.
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40       -y dir
41           Add the directory to the list of directories that should be
42           searched for include directories or libraries.
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VHIER ARGUMENTS

45       --help
46           Displays this message and program version and exits.
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48       --o file
49           Use the given filename for output instead of stdout.
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51       --cells
52           Show the module name of all cells in top-down order.
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54       --input-files
55           Show all input filenames.  Copying all of these files should result
56           in only those files needed to represent the entire design.
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58       --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009>
59           Set the language standard for the files.  This determines which
60           tokens are signals versus keywords, such as the ever-common "do"
61           (data-out signal, versus a do-while loop keyword).
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63       --resolve-files
64           Show resolved filenames passed on the command line.  This will
65           convert raw module and filenames without paths to include the
66           library search path directory.  Output filenames will be in the
67           same order as passed on the command line.  Unlike --input-files or
68           --module-files, hierarchy is not traversed.
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70       --module-files
71           Show all module filenames in top-down order.  Child modules will
72           always appear as low as possible, so that reversing the list will
73           allow bottom-up processing of modules.  Unlike input-files, header
74           files are not included.
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76       --modules
77           Show all module names.
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79       --nomissing
80           Do not complain about references to missing modules.
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82       --missing-modules
83           With --nomissing, show all modules that are not found.
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85       --top-module module
86           Start the report at the specified module name, ignoring all modules
87           that are not the one specified with --top-module or below, and
88           report an error if the --top-module specified does not exist.
89           Without this option vhier will report all modules, starting at the
90           module(s) that have no children below them.
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92           Note this option will not change the result of the --input-files
93           list, as the files needed to parse any design are independent of
94           which modules are used.
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96       --version
97           Displays program version and exits.
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DISTRIBUTION

100       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
101       software tool suite.  The latest version is available from CPAN and
102       from http://www.veripool.org/verilog-perl
103       <http://www.veripool.org/verilog-perl>.
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105       Copyright 2005-2010 by Wilson Snyder.  This package is free software;
106       you can redistribute it and/or modify it under the terms of either the
107       GNU Lesser General Public License Version 3 or the Perl Artistic
108       License Version 2.0.
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AUTHORS

111       Wilson Snyder <wsnyder@wsnyder.org>
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