1GVHDL(1) User Commands GVHDL(1)
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6 gvhdl - Frontend to the VHDL compiler/simulator FreeHDL.
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9 gvhdl [OPTION] ... [VHDL_FILES] ... [OBJECT_FILES] ...
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12 FreeHDL is a compiler/simulator suite for the hardware description lan‐
13 guage VHDL. VHDL'93 as well as VHDL'87 standards are supported.
14 FreeHDL translates the original VHDL source FILEs into C++. Then, the
16 C++ source can be compiled and linked to the kernel to build the simu‐
17 lation program. Starting the generated executable will simulate the
18 corresponding VHDL model. The actual build process to generate the sim‐
19 ulator from the VHDL source is a complex process which is handled by
20 the gvhdl script.
21 VHDL_FILES is a list of VHDL source file names that must end with .vhdl
23 or .vhd. The first VHDL file name also determines the name of the simu‐
24 lator executable. This is, the final executable will be named after the
25 first VHDL file without the .vhdl or .vhd extension. Note that the
26 object files as well as the simulator will be created in the current
27 directory.
28 OBJECT_FILES specifies a list of object files that are linked to the
30 simulator executable. gvhdl considers all files that end with .o to be
31 object files. Typically, these object files are generated previously
32 (using option -c) from VHDL source code during a separate compilation
33 step.
34
36 -L VHDLLIB
37 Path to VHDL library root directory. Within this directory the
38 compiler search for a file named v2cc.libs. The mapping file
39 v2cc.libs translates library unit names to directories. Note
40 that more than one VHDLLIB may be provided.
41 -g Adds debug information to the executable. In detail, this
43 options associates the generated machine code to the correspond‐
44 ing lines in the VHDL source files.
45 -G Adds debug information to the executable but does not associate
47 machine code to VHDL source lines. This option is actually used
48 to debug the generated C++ code.
49 -c Do not generate simulator executable. Using this option, the
51 compiler translated VHDL source into executables and compiles
52 them into object code but does not generate a final simulator
53 executable. This option is especially useful to compile VHDL
54 packages.
55 -l LIBNAME
57 Associate the VHDL source code to VHDL library LIBNAME. As
58 default the library name WORK is used. This option is especially
59 important if VHDL components from several VHDL libraries shall
60 be build into the simulator. Note that in order to successfully
61 use a VHDL component from another than the current working
62 library, the corresponding VHDL files must be found by the com‐
63 piler using the mechanisms described in v2cc.libs. Further, com‐
64 ponents must be compiled with the appropriate -l LIBNAME option.
65 --relaxed-component-visibility
67 Allows invisible default bindings from WORK.
68 --libieee
70 Add the IEEE standard library files to the simulation exe‐
71 cutable.
72 ENVIRONMENT VARIABLES
75 V2CC_LIBRARY_PATH
77 The variable V2CC_LIBRARY_PATH consists of ":" separated file‐
78 names. In addition to the environment variable, you can use the
79 "-L libdir" command line option with v2cc. The directories
80 specified with "-L" are added in front of the ones specified by
81 V2CC_LIBRARY_PATH. In the final library path, they appear in
82 the same order as on the command line.
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85 Currently, FreeHDL does not support the entire VHDL'93 standard. The
86 following incomplete list gives an overview on what is currently not
87 supported:
88 - Individual association of formals of composite type are not sup‐
90 ported.
91 - Shared variables are not supported.
93 - Attributes transaction, quiet, stable and delayed are not supported.
95 - User defined attributes are not supported.
97 - Groups are not supported.
99 - Guarded signal assignments are not supported.
101 - Configurations are not supported.
103 - Currently, drivers cannot be switched off.
105
107 Use
108 gvhdl -c adder.vhdl
110 to build an object file for adder.vhdl. Note that adder.vhdl may con‐
112 tain several VHDL models.
113 gvhdl adder.vhdl
115 will generate a simulator for the last VHDL model found in adder.vhdl.
117 However, in this case, all VHDL components that area required to build
118 the simulator must be included in the VHDL source file.
119 gvhdl top.vhdl adder.o --libieee
121 generates a simulator for the last VHDL model found in top.vhdl by com‐
123 piling all models in top.vhdl and linking (the previously generated)
124 adder.o object file and the IEEE standard libraries to the executable.
125 gvhdl -c -l mylib adder.vhdl
127 will build an object file including all components provided in
129 adder.vhdl. However, in this case the components will be associated
130 with library mylib instead of the default library name work. Note that
131 option -l does only effect the generated C++ source code but does not
132 alter the place where the object files or executables are stored.
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135 After the simulator has been started a short summary of the available
136 commands is printed to the screen:
137 c <number> : execute cycles = execute <number> simulation cycles
139 n : next = execute next simulation cycle
140 q : quit = quit simulation
141 r <time> : run = execute simulation for <time>
142 d : dump = dump signals
143 doff : dump off = stop dumping signals
144 don : dump on = continue dumping signals
145 s : show = show signal values
146 dv : dump var = dump a signal from the signal lists
147 ds : dump show = shows the list of dumped signals
148 nds : number show = shows the number of dumped signals
149 dc [-f <filename>] [-t <timescale> <time unit>] [-cfg <translation
150 file>] [-q]
151 : configures dump process
152 Note that signals are dumped into a file (default file name is
154 "wave.dmp") in VCD format. This file format should be accepted by each
155 VCD waveform viewer. The file name is set to "wave.dmp" but may be
156 changed using "dc -f <new_file_name>". However, make sure to execute
157 "dc -f ..." before executing "d".
158
160 Simulation can be controlled via the command line parameter '-cmd
161 "cmd1; cmd2; ..."' where 'cmd1', 'cmd2', ... are simulation commands as
162 described in the previous section. Note that each command must be sepa‐
163 rated by ';'. E.g., executing
164 ./top -cmd "d;run 1000 ns;q;"
166 will start simulation program 'top', dump all signals and run simula‐
168 tion for 1000 ns. Finally, simulation is terminated. Actually, the last
169 command 'q;' is optional as the simulator automatically terminates as
170 soon as the last command has been executed.
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173 freehdl-v2cc(1), freehdl-config(1), v2cc.libs(5)
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176 The latest version of FreeHDL can always be obtained from www.free‐
177 hdl.seul.org
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180 Known bugs are documented within the BUGS file. If your report
181 addresses a parser related topic then contact Marius Vollmer
182 <mvo@zagadka.ping.de>. If it is related to the code generator or com‐
183 piler then send an email to Edwin Naroska <edwin@ds.e-technik.uni-dort‐
184 mund.de>. If your are not sure send it to Edwin. He will take care of
185 forwarding your report to the appropriate recipient.
186
188 Edwin Naroska © 1999, 2000, 2001, 2002, 2003, 2004, 2005 <edwin@ds.e-
189 technik.uni-dortmund.de>
190 This is free software; see the source for copying conditions. There is
192 NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
193 PURPOSE.
194
196 Written by Marius Vollmer <mvo@zagadka.ping.de> and Edwin Naroska
197 <edwin@ds.e-technik.uni-dortmund.de>.
198Debian/GNU Linux December 2005 GVHDL(1)