1TBLGEN(1)                            LLVM                            TBLGEN(1)
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NAME

6       tblgen - Target Description To C++ Code Generator
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SYNOPSIS

9       tblgen [options] [filename]
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DESCRIPTION

12       tblgen  translates  from  target  description (.td) files into C++ code
13       that can be included in the definition of an LLVM target library.  Most
14       users  of  LLVM  will  not  need  to  use this program.  It is only for
15       assisting with writing an LLVM target backend.
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17       The input and output of tblgen is beyond the scope of this short intro‐
18       duction; please see the introduction to TableGen.
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20       The  filename argument specifies the name of a Target Description (.td)
21       file to read as input.
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OPTIONS

24       -help  Print a summary of command line options.
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26       -o filename
27              Specify the output file name.  If filename  is  -,  then  tblgen
28              sends its output to standard output.
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30       -I directory
31              Specify  where to find other target description files for inclu‐
32              sion.  The directory value should be a full or partial path to a
33              directory that contains target description files.
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35       -asmparsernum N
36              Make -gen-asm-parser emit assembly writer number N.
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38       -asmwriternum N
39              Make -gen-asm-writer emit assembly writer number N.
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41       -class className
42              Print the enumeration list for this class.
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44       -print-records
45              Print all records to standard output (default).
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47       -dump-json
48              Print a JSON representation of all records, suitable for further
49              automated processing.
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51       -print-enums
52              Print enumeration values for a class.
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54       -print-sets
55              Print expanded sets for testing DAG exprs.
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57       -gen-emitter
58              Generate machine code emitter.
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60       -gen-register-info
61              Generate registers and register classes info.
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63       -gen-instr-info
64              Generate instruction descriptions.
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66       -gen-asm-writer
67              Generate the assembly writer.
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69       -gen-disassembler
70              Generate disassembler.
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72       -gen-pseudo-lowering
73              Generate pseudo instruction lowering.
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75       -gen-dag-isel
76              Generate a DAG (Directed Acycle Graph) instruction selector.
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78       -gen-asm-matcher
79              Generate assembly instruction matcher.
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81       -gen-dfa-packetizer
82              Generate DFA Packetizer for VLIW targets.
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84       -gen-fast-isel
85              Generate a "fast" instruction selector.
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87       -gen-subtarget
88              Generate subtarget enumerations.
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90       -gen-intrinsic-enums
91              Generate intrinsic enums.
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93       -gen-intrinsic-impl
94              Generate intrinsic implementation.
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96       -gen-tgt-intrinsic
97              Generate target intrinsic information.
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99       -gen-enhanced-disassembly-info
100              Generate enhanced disassembly info.
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102       -version
103              Show the version number of this program.
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EXIT STATUS

106       If tblgen succeeds, it will  exit  with  0.   Otherwise,  if  an  error
107       occurs, it will exit with a non-zero value.
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AUTHOR

110       Maintained by The LLVM Team (http://llvm.org/).
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113       2003-2019, LLVM Project
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1187                                 2019-03-19                         TBLGEN(1)
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