1VASY(5) VHDL subset of VASY. VASY(5)
2
6 vasy VHDL RTL subset.
7
10 This document describes the VHDL subset accepted by VASY for RTL
11 descriptions.
12 CONCURRENT STATEMENTS
15 In an RTL architecture most of the concurrent statements are supported.
16 Allowed concurrent statements are:
19 block
20 concurrent assertion
21 process
22 concurrent signal assignment
23 component instantiation statement
24 generate statement
25 SEQUENTIAL STATEMENTS
28 Inside a process, all sequential statements including loops, signal
29 assignment, variable assignment are supported.
30 TYPE
33 All types useful for synthesis are accepted (IEEE-1164 and
34 IEEE-1076.3), and all types defined in the VHDL Alliance subset (see
35 vbe(5) for more details).
36 OPERATORS
39 All operators useful for synthesis are accepted, such as arithmetic,
40 logical and relationnal operators (IEEE-1164 and IEEE-1076.3), and
41 those defined in the VHDL Alliance subset (see vbe(5) for more
42 details).
43 HARDWARE DESCRIPTION EXAMPLES
46 A MULTIPLEXER may be described as follow:
48 library IEEE;
50 use IEEE.std_logic_1164.all;
51 entity mux is
52 port(
53 sel,a,b : in std_logic;
54 mux_out : out std_logic );
55 end mux;
56 architecture rtl_1 of mux is
58 begin
59 process( sel,a,b )
60 begin
61 if (sel='1') then mux_out <= a;
62 else mux_out <= b;
63 end if;
64 end process;
65 end rtl_1;
66 architecture rtl_2 of mux is
68 begin
69 mux_out <= a when sel='1' else b;
70 end rtl_2;
71 A LATCH may be described as follow:
74 library IEEE;
76 use IEEE.std_logic_1164.all;
77 entity latch is
78 port(
79 en,a : in std_logic;
80 latch_out : out std_logic );
81 end latch;
82 architecture rtl_1 of latch is
84 begin
85 process( en, a )
86 begin
87 if (en='1') then latch_out <= a;
88 end if;
89 end process;
90 end rtl_1;
91 A D-FLIP-FLOP may be described as follow:
94 library IEEE;
96 use IEEE.std_logic_1164.all;
97 entity d_ff is
98 port(
99 ck,a : in std_logic;
100 d_ff_out : out std_logic );
101 end d_ff;
102 architecture rtl_1 of d_ff is
104 begin
105 process( ck )
106 begin
107 if (ck='1') then d_ff_out <= a;
108 end if;
109 end process;
110 end rtl_1;
111 architecture rtl_2 of d_ff is
113 begin
114 process( ck )
115 begin
116 if (ck='1' and ck'event)
117 then d_ff_out <= a;
118 end if;
119 end process;
120 end rtl_2;
121 architecture rtl_3 of d_ff is
123 begin
124 process
125 begin
126 wait until ck='1';
127 d_ff_out <= a;
128 end process;
129 end rtl_3;
130 A TRISTATE BUFFER may be described as follow:
133 library IEEE;
135 use IEEE.std_logic_1164.all;
136 entity trs is
137 port(
138 en,a : in std_logic;
139 trs_out : out std_logic );
140 end trs;
141 architecture rtl_1 of trs is
143 begin
144 process( en,a )
145 begin
146 if (en='1') then trs_out <= a;
147 else trs_out <= 'Z';
148 end if;
149 end process;
150 end rtl_1;
151 architecture rtl_2 of d_ff is
153 begin
154 trs_out <= a when en='1' else 'Z';
155 end rtl_2;
156 A RAM may be described as follow:
159 library IEEE;
161 use IEEE.std_logic_1164.all;
162 use IEEE.numeric_std.all;
163 entity ram is
165 port( clk,wr : in std_logic;
166 adr : std_logic_vector(1 downto 0);
167 i0 : in std_logic_vector(3 downto 0);
168 o0 : out std_logic_vector(3 downto 0)
169 );
170 end ram;
171 architecture rtl_1 of ram is
173 type my_array is array (0 to 3) of std_logic_vector(3 downto 0);
174 signal s : my_array;
175 begin
176 process
177 begin
178 wait until (clk='0' and clk'event);
179 if (wr='1')
180 then s(to_integer(unsigned(adr))) <= I0;
181 end if;
182 end process;
183 o0 <= s(to_integer(unsigned(adr)));
184 end rtl_1;
185 A ROM may be described as follow:
188 library IEEE;
190 use IEEE.std_logic_1164.all;
191 use IEEE.numeric_std.all;
192 entity rom is
194 port( adr : in std_logic_vector(1 downto 0);
195 o0 : out std_logic_vector(3 downto 0)
196 );
197 end rom;
198 architecture rtl_1 of rom is
200 subtype my_word is std_logic_vector(3 downto 0);
201 type my_array is array (0 to 3) of my_word;
202 constant s : my_array := ( "0000", "0001", "0010", "0011" );
203 begin
204 o0 <= s(to_integer(unsigned(adr)));
205 end rtl_1;
206 A PRIORITY DECODER may be described as follow:
209 library IEEE;
211 use IEEE.std_logic_1164.all;
212 use IEEE.numeric_std.all;
213 entity decod is
215 port( A : in std_logic_vector(3 downto 0);
216 B : out std_logic_vector(2 downto 0));
217 end decod;
218 architecture rtl_1 of decod is
219 begin
220 process( a )
221 begin
222 b <= "111";
223 for i in a'range -- Static For Loop are unrolled !
224 loop
225 exit when a(i)='1';
226 b <= std_logic_vector(to_unsigned(i,3));
227 end loop;
228 end process;
229 end rtl_1;
230
233 vasy(1), vbe(5), vhdl(5), vst(5), boom(1), loon(1), boog(1), asimut(1),
234 proof(1)
235ASIM/LIP6 December 11, 1999 VASY(5)