1VBE(5) VHDL subset of ASIM/LIP6/CAO-VLSI lab. VBE(5)
2
6 vbe
7 VHDL behavioural subset.
8
11 This document describes the ALLIANCE VHDL subset for behavioural data
12 flow descriptions.
13 CONCURRENT STATEMENTS
16 In a data flow architecture only concurrent statements (except process)
17 are supported. All sequential statements including loops, signal
18 assignment, etc .. are to be banished.
19 Allowed concurrent statements are:
22 simple signal assignment
23 conditional signal assignment
24 selected signal assignment
25 concurrent assert statement
26 block statement
27 BUSES
30 When using concurrent statements, an ordinary signal can be assigned
31 only once. The value of the signal must be explicitly defined by the
32 signal assignment (for example, in a selected signal assignment the
33 value of the target signal is to be defined for every value that the
34 select expression can take).
35 The above constraint may be felt as a hard restriction when designing
38 distributed controlled hardware (precharged line, distributed multi‐
39 plexer, etc ...). To hurdle this, VHDL uses a special feature: guarded-
40 resolved signals.
41 A resolved signal is a signal declared with a resolved subtype (see
44 vhdl(5)). A resolved subtype is a type combined with a resolution
45 function. A resolved signal can be assigned by multiple signal assign‐
46 ments. Depending on the value of each driver, the resolution function
47 determines the effective value of the signal.
48 A guarded signal is a resolved signal with drivers that can be dis‐
51 conected. A guarded signal must be assigned inside a block statement
52 through a guarded signal assignment.
53 A distributed multiplexer may be described as :
56 signal Distributed_Mux : mux_bit bus;
58 begin
60 first_driver_of_mux : block (Sel1 = '1')
62 begin
63 Distributed_Mux <= guarded Data1;
64 end block;
65 second_driver_of_mux : block (Sel2 = '1')
67 begin
68 Distributed_Mux <= guarded Data2;
69 end block;
70 LATCHES and REGISTERS
74 Sequential elements must be explicitly declared using the type reg_bit
75 or reg_vector (and must be of kind register). A sequential element must
76 be assigned inside a block statement by a guarded signal assignment.
77 Rising edge triggered D flip flop :
80 signal Reg : reg_bit register;
82 begin
84 flip_flop : block (ck = '1' and not ck'STABLE)
86 begin
87 Reg <= guarded Din;
88 end block;
89 Level sensitive latch:
92 signal Reg : reg_bit register;
94 begin
96 latch : block (ck = '1')
98 begin
99 Lat <= guarded Din;
100 end block;
101 In both cases, the guard expression must depend only on one signal if
104 the description is to be processed by the logic synthetizer (boom +
105 boog).
106 The following operators are only supported: not, and, or, xor, nor,
109 nand, &, =, /=
110 They can be applied on all types supported by the subset. Other stan‐
113 dard VHDL operators (+, -, >, <, ...) have not been implemented in the
114 present release.
115 TIMING
119 Timing information can be specified in behavioural descriptions using
120 after clauses. However, those delays are currently only used for simu‐
121 lation. After clauses are supported but not used for synthesis and for‐
122 mal proof.
123 After clauses in block statements (for guarded signal assignments) are
126 not supported for sequential elements (signals of kind register), but
127 supported for bus elements (signals of kind bus). This is because the
128 VHDL default disconnection time is null and this can generate unex‐
129 pected behavior for sequential elements.
130 In selected signal assignment, only uniform delays are supported (the
133 same After clause in all assignments).
134 Transport option is not supported. All delays are inertial delays.
137 ASSERT STATEMENT
139 Only two severity levels are supported in concurrent assert statements:
140 warning print a warning message if the assert condition is not
142 satisfied.
143 error print an error message if the assert condition is not
145 satisfied. Then, stop the simulation.
146 Assert statements are ignored by the logic synthesis tool.
149 DON'T CARE
152 A special feature has been introduced in order to allow "don't care"
153 specification when the logic synthtizer is targeted ( Beware : this
154 feature is incompatible with the IEEE VHDL standard !!).
155 An output can be assigned to the value 'D' (don't care). This is taken
158 into account by the logic synthesis tool in the optimization process.
159 When the value of an output is 'D' the logic synthesis tool may turn it
160 into a '1' or a '0'.
161 A 'D' value is understood as a '0' by the logic simulator (asimut).
164 ARRAIES
167 Arraies other than bit_vector, reg_vector, mux_vector and wor_vector
168 are not supported.
169
172 Here is the description of an adder with an accumulator register.
173 entity add_accu is
175 port (
176 clk : in bit;
177 command : in bit;
178 data_in : in bit_vector (31 downto 0);
179 data_out : out bit_vector (31 downto 0);
180 cry_out : out bit;
181 vdd : in bit;
182 vss : in bit
183 );
184 end add_accu;
185 architecture data_flow of add_accu is
187 signal eff_data : bit_vector (31 downto 0); -- effective operande
189 signal adder_out : bit_vector (31 downto 0); -- adder's result
190 signal adder_cry : bit_vector (32 downto 0); -- adder's carry
191 signal accum_reg : reg_vector (31 downto 0) register; -- accumulator
192 constant initialize : bit := '0';
194 constant accumulate : bit := '1';
195 begin
197 -- select the effective operand
199 with command select
201 eff_data <= X"0000_0000" when initialize,
202 accum_reg when accumulate;
203 -- compute the result out of the adder
205 adder_out <= eff_data xor data_in xor adder_cry;
207 adder_cry (0) <= '0';
208 adder_cry (32 downto 1) <= (eff_data and adder_cry (31 downto 0)) or
209 (data_in and adder_cry (31 downto 0)) or
210 (aff_data and data_in ) ;
211 -- write the result into the register on the rising edge of clk
213 write : block (clk = '1' and not clk'STABLE)
215 begin
216 accum_reg <= guarded adder_out;
217 end block;
218 -- assign outputs
220 cry_out <= adder_cry (32);
222 data_out <= accum_reg ;
223 -- check power supply
225 assert (vdd = '1' and vss = '0')
227 report "power sypply is missing"
228 severity ERROR;
229 end;
231
235 vhdl(5), vst(5), boom(1), loon(1), boog(1), asimut(1), proof(1)
236ASIM/LIP6 October 1, 1997 VBE(5)