1VHDL(5)             VHDL subset of ASIM/LIP6/CAO-VLSI lab.             VHDL(5)
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NAME

6       ALLIANCE VHDL Subset
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DESCRIPTION

10       The  ALLIANCE  VHDL subset is dedicated to digital synchronous circuits
11       design.  The same subset is used for:
12              logic simulation (asimut)
13              logic synthesis (boom, boog, loon)
14              functionnal abstraction (yagle)
15              formal proof (proof)
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18       The ALLIANCE VHDL subset is fully compatible with the IEEE  VHDL  stan‐
19       dard  Ref.   1076  (1987). That means that a VHDL description using the
20       ALLIANCE subset can be simulated with  any  full-VHDL  commercial  com‐
21       piler-simulator.
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24       Here follows the main restrictions of the ALLIANCE subset.
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27       The  VHDL  description  of a circuit is made of two separate parts: the
28       external view and the internal view.
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31       The external view defines the name of the circuit  and  its  interface.
32       The  interface  of a circuit is a list of ports. Each port is specified
33       by its name, its mode, its type, its constraint for an array  and,  its
34       kind.
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37       The  mode  of a port depends only on the manner the port is used inside
38       the circuit (in the internal view of the circuit). If the  value  of  a
39       port  is  to  be  read in the view of the description, the port must be
40       declared with the mode in. If the value of a port is to be  written  by
41       the internal view, the port must be declared with the mode out. If both
42       above conditions are satisfied the port must be declared with the  mode
43       inout.
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46       Only  structural  and  behavioural  data flow are supported as internal
47       view.
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50       In order to allow automatic translation from structural VHDL  to  other
51       netlist  formats  (EDIF,  ALLIANCE, COMPASS, ...) it is not possible to
52       mix behavioural and structural description. Of  course,  a  circuit,  a
53       subcircuit or a cell can have two different descriptions:
54              a structural view may be defined in a file with a .vst extension
55              (see vst(5)).
56              a behavioural data flow description may be  defined  in  a  file
57              with a .vbe extension (see vbe(5)).
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59       A  typical VHDL model will be made of a hierarcical structural descrip‐
60       tion (a hierarchy of structural files)  and,  for  each  leaf  cell,  a
61       behavioural description.
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64       In  a  behavioural  description,  only  concurrent  statements  (except
65       process) are supported.  Up  to  now,  sequential  statements  are  not
66       allowed by the ALLIANCE VHDL compiler.
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70       Timing  information  can be specified in behavioural descriptions using
71       After clauses. However, those delays are currently only used for  simu‐
72       lation. After clauses are supported but not used for synthesis and for‐
73       mal proof.
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76       A predefined set of types has been defined (other  user  defined  types
77       are not supported):
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79       bit            the predefined standard bit type ('0' or '1')
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81       bit_vector     array of bit
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83       mux_bit        a resolved subtype of bit using the mux resolution func‐
84                      tion. This function checks that only one driver is actu‐
85                      ally  connected  to a signal. The effective value of the
86                      signal is the value of the active driver. If all drivers
87                      are  disconnected,  the value of the signal is '1' (pull
88                      up). A signal of type mux_bit must be declared with  the
89                      kind bus.
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91       mux_vector     array of mux_bit
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93       wor_bit        a resolved subtype of bit using the wor resolution func‐
94                      tion. This function allows a signal be  driven  by  more
95                      than  one  driver.  All active drivers have to drive the
96                      same value. The effective value of  the  signal  is  the
97                      value  of  active  drivers.  If  all drivers are discon‐
98                      nected, the value of the signal is '1' (pull up). A sig‐
99                      nal of type wor_bit must be declared with the kind bus.
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101       wor_vector     array of wor_bit
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103       reg_bit        a resolved subtype of bit using the reg resolution func‐
104                      tion. This function checks that only one driver is actu‐
105                      ally  connected  to a signal. The effective value of the
106                      signal is the value of the active driver.  A  signal  of
107                      type  reg_bit  must  be  declared with the kind register
108                      (which makes the signal keep its previous value when all
109                      drivers are disconnected).
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111       reg_vector     array of reg_bit
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114       In  the  next ALLIANCE release the VHDL subset will be largely extended
115       (sequential statements, user defined types) .
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SEE ALSO

119       vst(5), vbe(5), asimut(1), boom(1), loon(1), boog(1), proof(1)
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126ASIM/LIP6                       October 1, 1997                        VHDL(5)