vst(5alc)

1VST(5)              VHDL subset of ASIM/LIP6/CAO-VLSI lab.              VST(5)
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NAME

6       vst
7       VHDL structural subset.
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DESCRIPTION

11       This  document  describes  the  ALLIANCE  VHDL  subset  for  structural
12       descriptions.
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15       The declaration  part  of  a  structural  description  includes  signal
16       decalarations and component declarations.
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19       An internal signal can be declared of any type supported by the present
20       VHDL subset except reg_bit and reg_vector.
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23       A component must be declared with exactly the same port description  as
24       in  its  entity  specification.  This  means that local ports are to be
25       declared with the same name, type and kind and in the same order.
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28       A structural description is a set  of  component  instantiation  state‐
29       ments.   Instances' ports are connected to each other trough signals in
30       a port map specification. Both explicit and implicit port map  specifi‐
31       cations are supported by the ALLIANCE VHDL subset.
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34       The  present  version  of  the VHDL compiler does not allow unconnected
35       ports (the open mode is not supported).
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38       Only the concatenation operator (&) can be  used  in  the  actual  part
39       (effective signal conntected to a formal port) of a port map specifica‐
40       tion.
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EXAMPLES

44       Here is the description of an adder with an accumulator register.
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46       entity add_accu is
47       port (
48         clk      : in  bit;
49         command  : in  bit;
50         data_in  : in  bit_vector (31 downto 0);
51         data_out : out bit_vector (31 downto 0);
52         cry_out  : out bit;
53         vdd      : in  bit;
54         vss      : in  bit
55         );
56       end add_accu;
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58       architecture structural of add_accu is
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60       signal eff_data  : bit_vector (31 downto 0);      -- effective operande
61       signal adder_out : bit_vector (31 downto 0);      -- adder's result
62       signal accu_out  : bit_vector (31 downto 0);      -- accumulator
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64       component adder
65       port (a   : in  bit_vector (31 downto 0);
66             b   : in  bit_vector (31 downto 0);
67             res : out bit_vector (31 downto 0));
68       end component;
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70       component and_32
71       port (a   : in  bit_vector (31 downto 0);
72             cmd : in  bit;
73             res : out bit_vector (31 downto 0));
74       end component;
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76       component falling_edge_reg
77       port (din  : in  bit_vector (31 downto 0);
78             clk  : in  bit;
79             dout : out bit_vector (31 downto 0));
80       end component;
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82       begin
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84         my_adder : adder
85         port map (a => eff_data, b => accu_out, res => adder_out);
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87         my_mux   : and_32
88         port map (cmd => command, a => accu_out, res => eff_data);
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90         my_reg   : falling_edge_reg
91         port map (din => adder_out, clk => clk, dout => accu_out);
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93       end;
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NAME

DESCRIPTION

EXAMPLES

SEE ALSO