1AS(1)                        GNU Development Tools                       AS(1)
2
3
4

NAME

6       AS - the portable GNU assembler.
7

SYNOPSIS

9       as [-a[cdghlns][=file]] [--alternate] [-D]
10        [--compress-debug-sections]  [--nocompress-debug-sections]
11        [--debug-prefix-map old=new]
12        [--defsym sym=val] [-f] [-g] [--gstabs]
13        [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14        [--help] [-I dir] [-J]
15        [-K] [-L] [--listing-lhs-width=NUM]
16        [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
17        [--listing-cont-lines=NUM] [--keep-locals] [-o
18        objfile] [-R] [--reduce-memory-overheads] [--statistics]
19        [-v] [-version] [--version] [-W] [--warn]
20        [--fatal-warnings] [-w] [-x] [-Z] [@FILE]
21        [--size-check=[error|warning]]
22        [--target-help] [target-options]
23        [--|files ...]
24
25       Target AArch64 options:
26          [-EB|-EL]
27          [-mabi=ABI]
28
29       Target Alpha options:
30          [-mcpu]
31          [-mdebug | -no-mdebug]
32          [-replace | -noreplace]
33          [-relax] [-g] [-Gsize]
34          [-F] [-32addr]
35
36       Target ARC options:
37          [-marc[5|6|7|8]]
38          [-EB|-EL]
39
40       Target ARM options:
41          [-mcpu=processor[+extension...]]
42          [-march=architecture[+extension...]]
43          [-mfpu=floating-point-format]
44          [-mfloat-abi=abi]
45          [-meabi=ver]
46          [-mthumb]
47          [-EB|-EL]
48          [-mapcs-32|-mapcs-26|-mapcs-float|
49           -mapcs-reentrant]
50          [-mthumb-interwork] [-k]
51
52       Target Blackfin options:
53          [-mcpu=processor[-sirevision]]
54          [-mfdpic]
55          [-mno-fdpic]
56          [-mnopic]
57
58       Target CRIS options:
59          [--underscore | --no-underscore]
60          [--pic] [-N]
61          [--emulation=criself | --emulation=crisaout]
62          [--march=v0_v10 | --march=v10 | --march=v32 |
63       --march=common_v10_v32]
64
65       Target D10V options:
66          [-O]
67
68       Target D30V options:
69          [-O|-n|-N]
70
71       Target EPIPHANY options:
72          [-mepiphany|-mepiphany16]
73
74       Target H8/300 options:
75          [-h-tick-hex]
76
77       Target i386 options:
78          [--32|--x32|--64] [-n]
79          [-march=CPU[+EXTENSION...]] [-mtune=CPU]
80
81       Target i960 options:
82          [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
83           -AKC|-AMC]
84          [-b] [-no-relax]
85
86       Target IA-64 options:
87          [-mconstant-gp|-mauto-pic]
88          [-milp32|-milp64|-mlp64|-mp64]
89          [-mle|mbe]
90          [-mtune=itanium1|-mtune=itanium2]
91          [-munwind-check=warning|-munwind-check=error]
92          [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
93          [-x|-xexplicit] [-xauto] [-xdebug]
94
95       Target IP2K options:
96          [-mip2022|-mip2022ext]
97
98       Target M32C options:
99          [-m32c|-m16c] [-relax] [-h-tick-hex]
100
101       Target M32R options:
102          [--m32rx|--[no-]warn-explicit-parallel-conflicts|
103          --W[n]p]
104
105       Target M680X0 options:
106          [-l] [-m68000|-m68010|-m68020|...]
107
108       Target M68HC11 options:
109          [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
110          [-mshort|-mlong]
111          [-mshort-double|-mlong-double]
112          [--force-long-branches] [--short-branches]
113          [--strict-direct-mode] [--print-insn-syntax]
114          [--print-opcodes] [--generate-example]
115
116       Target MCORE options:
117          [-jsri2bsr] [-sifilter] [-relax]
118          [-mcpu=[210|340]]
119
120       Target Meta options:
121          [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
122
123       Target MIPS options:
124          [-nocpp] [-EL] [-EB] [-O[optimization level]]
125          [-g[debug level]] [-G num] [-KPIC] [-call_shared]
126          [-non_shared] [-xgot [-mvxworks-pic]
127          [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
128          [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
129          [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
130          [-mips64] [-mips64r2]
131          [-construct-floats] [-no-construct-floats]
132          [-mnan=encoding]
133          [-trap] [-no-break] [-break] [-no-trap]
134          [-mips16] [-no-mips16]
135          [-mmicromips] [-mno-micromips]
136          [-msmartmips] [-mno-smartmips]
137          [-mips3d] [-no-mips3d]
138          [-mdmx] [-no-mdmx]
139          [-mdsp] [-mno-dsp]
140          [-mdspr2] [-mno-dspr2]
141          [-mmt] [-mno-mt]
142          [-mmcu] [-mno-mcu]
143          [-minsn32] [-mno-insn32]
144          [-mfix7000] [-mno-fix7000]
145          [-mfix-vr4120] [-mno-fix-vr4120]
146          [-mfix-vr4130] [-mno-fix-vr4130]
147          [-mdebug] [-no-mdebug]
148          [-mpdr] [-mno-pdr]
149
150       Target MMIX options:
151          [--fixed-special-register-names] [--globalize-symbols]
152          [--gnu-syntax] [--relax] [--no-predefined-symbols]
153          [--no-expand] [--no-merge-gregs] [-x]
154          [--linker-allocated-gregs]
155
156       Target Nios II options:
157          [-relax-all] [-relax-section] [-no-relax]
158          [-EB] [-EL]
159
160       Target PDP11 options:
161          [-mpic|-mno-pic] [-mall] [-mno-extensions]
162          [-mextension|-mno-extension]
163          [-mcpu] [-mmachine]
164
165       Target picoJava options:
166          [-mb|-me]
167
168       Target PowerPC options:
169          [-a32|-a64]
170          [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
171           -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
172           -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
173           -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
174           -mpower7|-mpwr7|-mpower8|-mpwr8|-ma2|-mcell|-mspe|-mtitan|-me300|-mcom]
175          [-many] [-maltivec|-mvsx|-mhtm|-mvle]
176          [-mregnames|-mno-regnames]
177          [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
178          [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
179          [-msolaris|-mno-solaris]
180          [-nops=count]
181
182       Target RX options:
183          [-mlittle-endian|-mbig-endian]
184          [-m32bit-doubles|-m64bit-doubles]
185          [-muse-conventional-section-names]
186          [-msmall-data-limit]
187          [-mpid]
188          [-mrelax]
189          [-mint-register=number]
190          [-mgcc-abi|-mrx-abi]
191
192       Target s390 options:
193          [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
194          [-mregnames|-mno-regnames]
195          [-mwarn-areg-zero]
196
197       Target SCORE options:
198          [-EB][-EL][-FIXDD][-NWARN]
199          [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
200          [-march=score7][-march=score3]
201          [-USE_R1][-KPIC][-O0][-G num][-V]
202
203       Target SPARC options:
204          [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
205           -Av8plus|-Av8plusa|-Av9|-Av9a]
206          [-xarch=v8plus|-xarch=v8plusa] [-bump]
207          [-32|-64]
208
209       Target TIC54X options:
210        [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
211        [-merrors-to-file <filename>|-me <filename>]
212
213       Target TIC6X options:
214          [-march=arch] [-mbig-endian|-mlittle-endian]
215          [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
216          [-mpic|-mno-pic]
217
218       Target TILE-Gx options:
219          [-m32|-m64][-EB][-EL]
220
221       Target Xtensa options:
222        [--[no-]text-section-literals] [--[no-]absolute-literals]
223        [--[no-]target-align] [--[no-]longcalls]
224        [--[no-]transform]
225        [--rename-section oldname=newname]
226
227       Target Z80 options:
228         [-z80] [-r800]
229         [ -ignore-undocumented-instructions] [-Wnud]
230         [ -ignore-unportable-instructions] [-Wnup]
231         [ -warn-undocumented-instructions] [-Wud]
232         [ -warn-unportable-instructions] [-Wup]
233         [ -forbid-undocumented-instructions] [-Fud]
234         [ -forbid-unportable-instructions] [-Fup]
235

DESCRIPTION

237       GNU as is really a family of assemblers.  If you use (or have used) the
238       GNU assembler on one architecture, you should find a fairly similar
239       environment when you use it on another architecture.  Each version has
240       much in common with the others, including object file formats, most
241       assembler directives (often called pseudo-ops) and assembler syntax.
242
243       as is primarily intended to assemble the output of the GNU C compiler
244       "gcc" for use by the linker "ld".  Nevertheless, we've tried to make as
245       assemble correctly everything that other assemblers for the same
246       machine would assemble.  Any exceptions are documented explicitly.
247       This doesn't mean as always uses the same syntax as another assembler
248       for the same architecture; for example, we know of several incompatible
249       versions of 680x0 assembly language syntax.
250
251       Each time you run as it assembles exactly one source program.  The
252       source program is made up of one or more files.  (The standard input is
253       also a file.)
254
255       You give as a command line that has zero or more input file names.  The
256       input files are read (from left file name to right).  A command line
257       argument (in any position) that has no special meaning is taken to be
258       an input file name.
259
260       If you give as no file names it attempts to read one input file from
261       the as standard input, which is normally your terminal.  You may have
262       to type ctl-D to tell as there is no more program to assemble.
263
264       Use -- if you need to explicitly name the standard input file in your
265       command line.
266
267       If the source is empty, as produces a small, empty object file.
268
269       as may write warnings and error messages to the standard error file
270       (usually your terminal).  This should not happen when  a compiler runs
271       as automatically.  Warnings report an assumption made so that as could
272       keep assembling a flawed program; errors report a grave problem that
273       stops the assembly.
274
275       If you are invoking as via the GNU C compiler, you can use the -Wa
276       option to pass arguments through to the assembler.  The assembler
277       arguments must be separated from each other (and the -Wa) by commas.
278       For example:
279
280               gcc -c -g -O -Wa,-alh,-L file.c
281
282       This passes two options to the assembler: -alh (emit a listing to
283       standard output with high-level and assembly source) and -L (retain
284       local symbols in the symbol table).
285
286       Usually you do not need to use this -Wa mechanism, since many compiler
287       command-line options are automatically passed to the assembler by the
288       compiler.  (You can call the GNU compiler driver with the -v option to
289       see precisely what options it passes to each compilation pass,
290       including the assembler.)
291

OPTIONS

293       @file
294           Read command-line options from file.  The options read are inserted
295           in place of the original @file option.  If file does not exist, or
296           cannot be read, then the option will be treated literally, and not
297           removed.
298
299           Options in file are separated by whitespace.  A whitespace
300           character may be included in an option by surrounding the entire
301           option in either single or double quotes.  Any character (including
302           a backslash) may be included by prefixing the character to be
303           included with a backslash.  The file may itself contain additional
304           @file options; any such options will be processed recursively.
305
306       -a[cdghlmns]
307           Turn on listings, in any of a variety of ways:
308
309           -ac omit false conditionals
310
311           -ad omit debugging directives
312
313           -ag include general information, like as version and options passed
314
315           -ah include high-level source
316
317           -al include assembly
318
319           -am include macro expansions
320
321           -an omit forms processing
322
323           -as include symbols
324
325           =file
326               set the name of the listing file
327
328           You may combine these options; for example, use -aln for assembly
329           listing without forms processing.  The =file option, if used, must
330           be the last one.  By itself, -a defaults to -ahls.
331
332       --alternate
333           Begin in alternate macro mode.
334
335       --compress-debug-sections
336           Compress DWARF debug sections using zlib.  The debug sections are
337           renamed to begin with .zdebug, and the resulting object file may
338           not be compatible with older linkers and object file utilities.
339
340       --nocompress-debug-sections
341           Do not compress DWARF debug sections.  This is the default.
342
343       -D  Ignored.  This option is accepted for script compatibility with
344           calls to other assemblers.
345
346       --debug-prefix-map old=new
347           When assembling files in directory old, record debugging
348           information describing them as in new instead.
349
350       --defsym sym=value
351           Define the symbol sym to be value before assembling the input file.
352           value must be an integer constant.  As in C, a leading 0x indicates
353           a hexadecimal value, and a leading 0 indicates an octal value.  The
354           value of the symbol can be overridden inside a source file via the
355           use of a ".set" pseudo-op.
356
357       -f  "fast"---skip whitespace and comment preprocessing (assume source
358           is compiler output).
359
360       -g
361       --gen-debug
362           Generate debugging information for each assembler source line using
363           whichever debug format is preferred by the target.  This currently
364           means either STABS, ECOFF or DWARF2.
365
366       --gstabs
367           Generate stabs debugging information for each assembler line.  This
368           may help debugging assembler code, if the debugger can handle it.
369
370       --gstabs+
371           Generate stabs debugging information for each assembler line, with
372           GNU extensions that probably only gdb can handle, and that could
373           make other debuggers crash or refuse to read your program.  This
374           may help debugging assembler code.  Currently the only GNU
375           extension is the location of the current working directory at
376           assembling time.
377
378       --gdwarf-2
379           Generate DWARF2 debugging information for each assembler line.
380           This may help debugging assembler code, if the debugger can handle
381           it.  Note---this option is only supported by some targets, not all
382           of them.
383
384       --gdwarf-sections
385           Instead of creating a .debug_line section, create a series of
386           .debug_line.foo sections where foo is the name of the corresponding
387           code section.  For example a code section called .text.func will
388           have its dwarf line number information placed into a section called
389           .debug_line.text.func.  If the code section is just called .text
390           then debug line section will still be called just .debug_line
391           without any suffix.
392
393       --size-check=error
394       --size-check=warning
395           Issue an error or warning for invalid ELF .size directive.
396
397       --help
398           Print a summary of the command line options and exit.
399
400       --target-help
401           Print a summary of all target specific options and exit.
402
403       -I dir
404           Add directory dir to the search list for ".include" directives.
405
406       -J  Don't warn about signed overflow.
407
408       -K  Issue warnings when difference tables altered for long
409           displacements.
410
411       -L
412       --keep-locals
413           Keep (in the symbol table) local symbols.  These symbols start with
414           system-specific local label prefixes, typically .L for ELF systems
415           or L for traditional a.out systems.
416
417       --listing-lhs-width=number
418           Set the maximum width, in words, of the output data column for an
419           assembler listing to number.
420
421       --listing-lhs-width2=number
422           Set the maximum width, in words, of the output data column for
423           continuation lines in an assembler listing to number.
424
425       --listing-rhs-width=number
426           Set the maximum width of an input source line, as displayed in a
427           listing, to number bytes.
428
429       --listing-cont-lines=number
430           Set the maximum number of lines printed in a listing for a single
431           line of input to number + 1.
432
433       -o objfile
434           Name the object-file output from as objfile.
435
436       -R  Fold the data section into the text section.
437
438           Set the default size of GAS's hash tables to a prime number close
439           to number.  Increasing this value can reduce the length of time it
440           takes the assembler to perform its tasks, at the expense of
441           increasing the assembler's memory requirements.  Similarly reducing
442           this value can reduce the memory requirements at the expense of
443           speed.
444
445       --reduce-memory-overheads
446           This option reduces GAS's memory requirements, at the expense of
447           making the assembly processes slower.  Currently this switch is a
448           synonym for --hash-size=4051, but in the future it may have other
449           effects as well.
450
451       --statistics
452           Print the maximum space (in bytes) and total time (in seconds) used
453           by assembly.
454
455       --strip-local-absolute
456           Remove local absolute symbols from the outgoing symbol table.
457
458       -v
459       -version
460           Print the as version.
461
462       --version
463           Print the as version and exit.
464
465       -W
466       --no-warn
467           Suppress warning messages.
468
469       --fatal-warnings
470           Treat warnings as errors.
471
472       --warn
473           Don't suppress warning messages or treat them as errors.
474
475       -w  Ignored.
476
477       -x  Ignored.
478
479       -Z  Generate an object file even after errors.
480
481       -- | files ...
482           Standard input, or source files to assemble.
483
484       The following options are available when as is configured for the
485       64-bit mode of the ARM Architecture (AArch64).
486
487       -EB This option specifies that the output generated by the assembler
488           should be marked as being encoded for a big-endian processor.
489
490       -EL This option specifies that the output generated by the assembler
491           should be marked as being encoded for a little-endian processor.
492
493       -mabi=abi
494           Specify which ABI the source code uses.  The recognized arguments
495           are: "ilp32" and "lp64", which decides the generated object file in
496           ELF32 and ELF64 format respectively.  The default is "lp64".
497
498       The following options are available when as is configured for an Alpha
499       processor.
500
501       -mcpu
502           This option specifies the target processor.  If an attempt is made
503           to assemble an instruction which will not execute on the target
504           processor, the assembler may either expand the instruction as a
505           macro or issue an error message.  This option is equivalent to the
506           ".arch" directive.
507
508           The following processor names are recognized: 21064, "21064a",
509           21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
510           "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
511           "ev67", "ev68".  The special name "all" may be used to allow the
512           assembler to accept instructions valid for any Alpha processor.
513
514           In order to support existing practice in OSF/1 with respect to
515           ".arch", and existing practice within MILO (the Linux ARC
516           bootloader), the numbered processor names (e.g. 21064) enable the
517           processor-specific PALcode instructions, while the "electro-vlasic"
518           names (e.g. "ev4") do not.
519
520       -mdebug
521       -no-mdebug
522           Enables or disables the generation of ".mdebug" encapsulation for
523           stabs directives and procedure descriptors.  The default is to
524           automatically enable ".mdebug" when the first stabs directive is
525           seen.
526
527       -relax
528           This option forces all relocations to be put into the object file,
529           instead of saving space and resolving some relocations at assembly
530           time.  Note that this option does not propagate all symbol
531           arithmetic into the object file, because not all symbol arithmetic
532           can be represented.  However, the option can still be useful in
533           specific applications.
534
535       -replace
536       -noreplace
537           Enables or disables the optimization of procedure calls, both at
538           assemblage and at link time.  These options are only available for
539           VMS targets and "-replace" is the default.  See section 1.4.1 of
540           the OpenVMS Linker Utility Manual.
541
542       -g  This option is used when the compiler generates debug information.
543           When gcc is using mips-tfile to generate debug information for
544           ECOFF, local labels must be passed through to the object file.
545           Otherwise this option has no effect.
546
547       -Gsize
548           A local common symbol larger than size is placed in ".bss", while
549           smaller symbols are placed in ".sbss".
550
551       -F
552       -32addr
553           These options are ignored for backward compatibility.
554
555       The following options are available when as is configured for an ARC
556       processor.
557
558       -marc[5|6|7|8]
559           This option selects the core processor variant.
560
561       -EB | -EL
562           Select either big-endian (-EB) or little-endian (-EL) output.
563
564       The following options are available when as is configured for the ARM
565       processor family.
566
567       -mcpu=processor[+extension...]
568           Specify which ARM processor variant is the target.
569
570       -march=architecture[+extension...]
571           Specify which ARM architecture variant is used by the target.
572
573       -mfpu=floating-point-format
574           Select which Floating Point architecture is the target.
575
576       -mfloat-abi=abi
577           Select which floating point ABI is in use.
578
579       -mthumb
580           Enable Thumb only instruction decoding.
581
582       -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
583           Select which procedure calling convention is in use.
584
585       -EB | -EL
586           Select either big-endian (-EB) or little-endian (-EL) output.
587
588       -mthumb-interwork
589           Specify that the code has been generated with interworking between
590           Thumb and ARM code in mind.
591
592       -k  Specify that PIC code has been generated.
593
594       The following options are available when as is configured for the
595       Blackfin processor family.
596
597       -mcpu=processor[-sirevision]
598           This option specifies the target processor.  The optional
599           sirevision is not used in assembler.  It's here such that GCC can
600           easily pass down its "-mcpu=" option.  The assembler will issue an
601           error message if an attempt is made to assemble an instruction
602           which will not execute on the target processor.  The following
603           processor names are recognized: "bf504", "bf506", "bf512", "bf514",
604           "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
605           "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
606           implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
607           "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
608           "bf549", "bf549m", "bf561", and "bf592".
609
610       -mfdpic
611           Assemble for the FDPIC ABI.
612
613       -mno-fdpic
614       -mnopic
615           Disable -mfdpic.
616
617       See the info pages for documentation of the CRIS-specific options.
618
619       The following options are available when as is configured for a D10V
620       processor.
621
622       -O  Optimize output by parallelizing instructions.
623
624       The following options are available when as is configured for a D30V
625       processor.
626
627       -O  Optimize output by parallelizing instructions.
628
629       -n  Warn when nops are generated.
630
631       -N  Warn when a nop after a 32-bit multiply instruction is generated.
632
633       The following options are available when as is configured for an
634       Epiphany processor.
635
636       -mepiphany
637           Specifies that the both 32 and 16 bit instructions are allowed.
638           This is the default behavior.
639
640       -mepiphany16
641           Restricts the permitted instructions to just the 16 bit set.
642
643       The following options are available when as is configured for an H8/300
644       processor.  @chapter H8/300 Dependent Features
645
646   Options
647       The Renesas H8/300 version of "as" has one machine-dependent option:
648
649       -h-tick-hex
650           Support H'00 style hex constants in addition to 0x00 style.
651
652       The following options are available when as is configured for an i386
653       processor.
654
655       --32 | --x32 | --64
656           Select the word size, either 32 bits or 64 bits.  --32 implies
657           Intel i386 architecture, while --x32 and --64 imply AMD x86-64
658           architecture with 32-bit or 64-bit word-size respectively.
659
660           These options are only available with the ELF object file format,
661           and require that the necessary BFD support has been included (on a
662           32-bit platform you have to add --enable-64-bit-bfd to configure
663           enable 64-bit usage and use x86-64 as target platform).
664
665       -n  By default, x86 GAS replaces multiple nop instructions used for
666           alignment within code sections with multi-byte nop instructions
667           such as leal 0(%esi,1),%esi.  This switch disables the
668           optimization.
669
670       --divide
671           On SVR4-derived platforms, the character / is treated as a comment
672           character, which means that it cannot be used in expressions.  The
673           --divide option turns / into a normal character.  This does not
674           disable / at the beginning of a line starting a comment, or affect
675           using # for starting a comment.
676
677       -march=CPU[+EXTENSION...]
678           This option specifies the target processor.  The assembler will
679           issue an error message if an attempt is made to assemble an
680           instruction which will not execute on the target processor.  The
681           following processor names are recognized: "i8086", "i186", "i286",
682           "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
683           "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
684           "core", "core2", "corei7", "l1om", "k1om", "k6", "k6_2", "athlon",
685           "opteron", "k8", "amdfam10", "bdver1", "bdver2", "bdver3",
686           "btver1", "btver2", "generic32" and "generic64".
687
688           In addition to the basic instruction set, the assembler can be told
689           to accept various extension mnemonics.  For example,
690           "-march=i686+sse4+vmx" extends i686 with sse4 and vmx.  The
691           following extensions are currently supported: 8087, 287, 387,
692           "no87", "mmx", "nommx", "sse", "sse2", "sse3", "ssse3", "sse4.1",
693           "sse4.2", "sse4", "nosse", "avx", "avx2", "adx", "rdseed",
694           "prfchw", "smap", "mpx", "sha", "avx512f", "avx512cd", "avx512er",
695           "avx512pf", "noavx", "vmx", "vmfunc", "smx", "xsave", "xsaveopt",
696           "aes", "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma",
697           "movbe", "ept", "lzcnt", "hle", "rtm", "invpcid", "clflush", "lwp",
698           "fma4", "xop", "cx16", "syscall", "rdtscp", "3dnow", "3dnowa",
699           "sse4a", "sse5", "svme", "abm" and "padlock".  Note that rather
700           than extending a basic instruction set, the extension mnemonics
701           starting with "no" revoke the respective functionality.
702
703           When the ".arch" directive is used with -march, the ".arch"
704           directive will take precedent.
705
706       -mtune=CPU
707           This option specifies a processor to optimize for. When used in
708           conjunction with the -march option, only instructions of the
709           processor specified by the -march option will be generated.
710
711           Valid CPU values are identical to the processor list of -march=CPU.
712
713       -msse2avx
714           This option specifies that the assembler should encode SSE
715           instructions with VEX prefix.
716
717       -msse-check=none
718       -msse-check=warning
719       -msse-check=error
720           These options control if the assembler should check SSE
721           instructions.  -msse-check=none will make the assembler not to
722           check SSE instructions,  which is the default.  -msse-check=warning
723           will make the assembler issue a warning for any SSE instruction.
724           -msse-check=error will make the assembler issue an error for any
725           SSE instruction.
726
727       -mavxscalar=128
728       -mavxscalar=256
729           These options control how the assembler should encode scalar AVX
730           instructions.  -mavxscalar=128 will encode scalar AVX instructions
731           with 128bit vector length, which is the default.  -mavxscalar=256
732           will encode scalar AVX instructions with 256bit vector length.
733
734       -mevexlig=128
735       -mevexlig=256
736       -mevexlig=512
737           These options control how the assembler should encode length-
738           ignored (LIG) EVEX instructions.  -mevexlig=128 will encode LIG
739           EVEX instructions with 128bit vector length, which is the default.
740           -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
741           with 256bit and 512bit vector length, respectively.
742
743       -mevexwig=0
744       -mevexwig=1
745           These options control how the assembler should encode w-ignored
746           (WIG) EVEX instructions.  -mevexwig=0 will encode WIG EVEX
747           instructions with evex.w = 0, which is the default.  -mevexwig=1
748           will encode WIG EVEX instructions with evex.w = 1.
749
750       -mmnemonic=att
751       -mmnemonic=intel
752           This option specifies instruction mnemonic for matching
753           instructions.  The ".att_mnemonic" and ".intel_mnemonic" directives
754           will take precedent.
755
756       -msyntax=att
757       -msyntax=intel
758           This option specifies instruction syntax when processing
759           instructions.  The ".att_syntax" and ".intel_syntax" directives
760           will take precedent.
761
762       -mnaked-reg
763           This opetion specifies that registers don't require a % prefix.
764           The ".att_syntax" and ".intel_syntax" directives will take
765           precedent.
766
767       -madd-bnd-prefix
768           This option forces the assembler to add BND prefix to all branches,
769           even if such prefix was not explicitly specified in the source
770           code.
771
772       The following options are available when as is configured for the Intel
773       80960 processor.
774
775       -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
776           Specify which variant of the 960 architecture is the target.
777
778       -b  Add code to collect statistics about branches taken.
779
780       -no-relax
781           Do not alter compare-and-branch instructions for long
782           displacements; error if necessary.
783
784       The following options are available when as is configured for the
785       Ubicom IP2K series.
786
787       -mip2022ext
788           Specifies that the extended IP2022 instructions are allowed.
789
790       -mip2022
791           Restores the default behaviour, which restricts the permitted
792           instructions to just the basic IP2022 ones.
793
794       The following options are available when as is configured for the
795       Renesas M32C and M16C processors.
796
797       -m32c
798           Assemble M32C instructions.
799
800       -m16c
801           Assemble M16C instructions (the default).
802
803       -relax
804           Enable support for link-time relaxations.
805
806       -h-tick-hex
807           Support H'00 style hex constants in addition to 0x00 style.
808
809       The following options are available when as is configured for the
810       Renesas M32R (formerly Mitsubishi M32R) series.
811
812       --m32rx
813           Specify which processor in the M32R family is the target.  The
814           default is normally the M32R, but this option changes it to the
815           M32RX.
816
817       --warn-explicit-parallel-conflicts or --Wp
818           Produce warning messages when questionable parallel constructs are
819           encountered.
820
821       --no-warn-explicit-parallel-conflicts or --Wnp
822           Do not produce warning messages when questionable parallel
823           constructs are encountered.
824
825       The following options are available when as is configured for the
826       Motorola 68000 series.
827
828       -l  Shorten references to undefined symbols, to one word instead of
829           two.
830
831       -m68000 | -m68008 | -m68010 | -m68020 | -m68030
832       | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
833       | -m68333 | -m68340 | -mcpu32 | -m5200
834           Specify what processor in the 68000 family is the target.  The
835           default is normally the 68020, but this can be changed at
836           configuration time.
837
838       -m68881 | -m68882 | -mno-68881 | -mno-68882
839           The target machine does (or does not) have a floating-point
840           coprocessor.  The default is to assume a coprocessor for 68020,
841           68030, and cpu32.  Although the basic 68000 is not compatible with
842           the 68881, a combination of the two can be specified, since it's
843           possible to do emulation of the coprocessor instructions with the
844           main processor.
845
846       -m68851 | -mno-68851
847           The target machine does (or does not) have a memory-management unit
848           coprocessor.  The default is to assume an MMU for 68020 and up.
849
850       The following options are available when as is configured for an Altera
851       Nios II processor.
852
853       -relax-section
854           Replace identified out-of-range branches with PC-relative "jmp"
855           sequences when possible.  The generated code sequences are suitable
856           for use in position-independent code, but there is a practical
857           limit on the extended branch range because of the length of the
858           sequences.  This option is the default.
859
860       -relax-all
861           Replace branch instructions not determinable to be in range and all
862           call instructions with "jmp" and "callr" sequences (respectively).
863           This option generates absolute relocations against the target
864           symbols and is not appropriate for position-independent code.
865
866       -no-relax
867           Do not replace any branches or calls.
868
869       -EB Generate big-endian output.
870
871       -EL Generate little-endian output.  This is the default.
872
873       The following options are available when as is configured for a Meta
874       processor.
875
876       "-mcpu=metac11"
877           Generate code for Meta 1.1.
878
879       "-mcpu=metac12"
880           Generate code for Meta 1.2.
881
882       "-mcpu=metac21"
883           Generate code for Meta 2.1.
884
885       "-mfpu=metac21"
886           Allow code to use FPU hardware of Meta 2.1.
887
888       See the info pages for documentation of the MMIX-specific options.
889
890       The following options are available when as is configured for a PowerPC
891       processor.
892
893       -a32
894           Generate ELF32 or XCOFF32.
895
896       -a64
897           Generate ELF64 or XCOFF64.
898
899       -K PIC
900           Set EF_PPC_RELOCATABLE_LIB in ELF flags.
901
902       -mpwrx | -mpwr2
903           Generate code for POWER/2 (RIOS2).
904
905       -mpwr
906           Generate code for POWER (RIOS1)
907
908       -m601
909           Generate code for PowerPC 601.
910
911       -mppc, -mppc32, -m603, -m604
912           Generate code for PowerPC 603/604.
913
914       -m403, -m405
915           Generate code for PowerPC 403/405.
916
917       -m440
918           Generate code for PowerPC 440.  BookE and some 405 instructions.
919
920       -m464
921           Generate code for PowerPC 464.
922
923       -m476
924           Generate code for PowerPC 476.
925
926       -m7400, -m7410, -m7450, -m7455
927           Generate code for PowerPC 7400/7410/7450/7455.
928
929       -m750cl
930           Generate code for PowerPC 750CL.
931
932       -mppc64, -m620
933           Generate code for PowerPC 620/625/630.
934
935       -me500, -me500x2
936           Generate code for Motorola e500 core complex.
937
938       -me500mc
939           Generate code for Freescale e500mc core complex.
940
941       -me500mc64
942           Generate code for Freescale e500mc64 core complex.
943
944       -me5500
945           Generate code for Freescale e5500 core complex.
946
947       -me6500
948           Generate code for Freescale e6500 core complex.
949
950       -mspe
951           Generate code for Motorola SPE instructions.
952
953       -mtitan
954           Generate code for AppliedMicro Titan core complex.
955
956       -mppc64bridge
957           Generate code for PowerPC 64, including bridge insns.
958
959       -mbooke
960           Generate code for 32-bit BookE.
961
962       -ma2
963           Generate code for A2 architecture.
964
965       -me300
966           Generate code for PowerPC e300 family.
967
968       -maltivec
969           Generate code for processors with AltiVec instructions.
970
971       -mvle
972           Generate code for Freescale PowerPC VLE instructions.
973
974       -mvsx
975           Generate code for processors with Vector-Scalar (VSX) instructions.
976
977       -mhtm
978           Generate code for processors with Hardware Transactional Memory
979           instructions.
980
981       -mpower4, -mpwr4
982           Generate code for Power4 architecture.
983
984       -mpower5, -mpwr5, -mpwr5x
985           Generate code for Power5 architecture.
986
987       -mpower6, -mpwr6
988           Generate code for Power6 architecture.
989
990       -mpower7, -mpwr7
991           Generate code for Power7 architecture.
992
993       -mpower8, -mpwr8
994           Generate code for Power8 architecture.
995
996       -mcell
997       -mcell
998           Generate code for Cell Broadband Engine architecture.
999
1000       -mcom
1001           Generate code Power/PowerPC common instructions.
1002
1003       -many
1004           Generate code for any architecture (PWR/PWRX/PPC).
1005
1006       -mregnames
1007           Allow symbolic names for registers.
1008
1009       -mno-regnames
1010           Do not allow symbolic names for registers.
1011
1012       -mrelocatable
1013           Support for GCC's -mrelocatable option.
1014
1015       -mrelocatable-lib
1016           Support for GCC's -mrelocatable-lib option.
1017
1018       -memb
1019           Set PPC_EMB bit in ELF flags.
1020
1021       -mlittle, -mlittle-endian, -le
1022           Generate code for a little endian machine.
1023
1024       -mbig, -mbig-endian, -be
1025           Generate code for a big endian machine.
1026
1027       -msolaris
1028           Generate code for Solaris.
1029
1030       -mno-solaris
1031           Do not generate code for Solaris.
1032
1033       -nops=count
1034           If an alignment directive inserts more than count nops, put a
1035           branch at the beginning to skip execution of the nops.
1036
1037       See the info pages for documentation of the RX-specific options.
1038
1039       The following options are available when as is configured for the s390
1040       processor family.
1041
1042       -m31
1043       -m64
1044           Select the word size, either 31/32 bits or 64 bits.
1045
1046       -mesa
1047       -mzarch
1048           Select the architecture mode, either the Enterprise System
1049           Architecture (esa) or the z/Architecture mode (zarch).
1050
1051       -march=processor
1052           Specify which s390 processor variant is the target, g6, g6, z900,
1053           z990, z9-109, z9-ec, z10, z196, or zEC12.
1054
1055       -mregnames
1056       -mno-regnames
1057           Allow or disallow symbolic names for registers.
1058
1059       -mwarn-areg-zero
1060           Warn whenever the operand for a base or index register has been
1061           specified but evaluates to zero.
1062
1063       The following options are available when as is configured for a
1064       TMS320C6000 processor.
1065
1066       -march=arch
1067           Enable (only) instructions from architecture arch.  By default, all
1068           instructions are permitted.
1069
1070           The following values of arch are accepted: "c62x", "c64x", "c64x+",
1071           "c67x", "c67x+", "c674x".
1072
1073       -mdsbt
1074       -mno-dsbt
1075           The -mdsbt option causes the assembler to generate the
1076           "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1077           code is using DSBT addressing.  The -mno-dsbt option, the default,
1078           causes the tag to have a value of 0, indicating that the code does
1079           not use DSBT addressing.  The linker will emit a warning if objects
1080           of different type (DSBT and non-DSBT) are linked together.
1081
1082       -mpid=no
1083       -mpid=near
1084       -mpid=far
1085           The -mpid= option causes the assembler to generate the
1086           "Tag_ABI_PID" attribute with a value indicating the form of data
1087           addressing used by the code.  -mpid=no, the default, indicates
1088           position-dependent data addressing, -mpid=near indicates position-
1089           independent addressing with GOT accesses using near DP addressing,
1090           and -mpid=far indicates position-independent addressing with GOT
1091           accesses using far DP addressing.  The linker will emit a warning
1092           if objects built with different settings of this option are linked
1093           together.
1094
1095       -mpic
1096       -mno-pic
1097           The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1098           attribute with a value of 1, indicating that the code is using
1099           position-independent code addressing,  The "-mno-pic" option, the
1100           default, causes the tag to have a value of 0, indicating position-
1101           dependent code addressing.  The linker will emit a warning if
1102           objects of different type (position-dependent and position-
1103           independent) are linked together.
1104
1105       -mbig-endian
1106       -mlittle-endian
1107           Generate code for the specified endianness.  The default is little-
1108           endian.
1109
1110       The following options are available when as is configured for a TILE-Gx
1111       processor.
1112
1113       -m32 | -m64
1114           Select the word size, either 32 bits or 64 bits.
1115
1116       -EB | -EL
1117           Select the endianness, either big-endian (-EB) or little-endian
1118           (-EL).
1119
1120       The following options are available when as is configured for an Xtensa
1121       processor.
1122
1123       --text-section-literals | --no-text-section-literals
1124           Control the treatment of literal pools.  The default is
1125           --no-text-section-literals, which places literals in separate
1126           sections in the output file.  This allows the literal pool to be
1127           placed in a data RAM/ROM.  With --text-section-literals, the
1128           literals are interspersed in the text section in order to keep them
1129           as close as possible to their references.  This may be necessary
1130           for large assembly files, where the literals would otherwise be out
1131           of range of the "L32R" instructions in the text section.  These
1132           options only affect literals referenced via PC-relative "L32R"
1133           instructions; literals for absolute mode "L32R" instructions are
1134           handled separately.
1135
1136       --absolute-literals | --no-absolute-literals
1137           Indicate to the assembler whether "L32R" instructions use absolute
1138           or PC-relative addressing.  If the processor includes the absolute
1139           addressing option, the default is to use absolute "L32R"
1140           relocations.  Otherwise, only the PC-relative "L32R" relocations
1141           can be used.
1142
1143       --target-align | --no-target-align
1144           Enable or disable automatic alignment to reduce branch penalties at
1145           some expense in code size.    This optimization is enabled by
1146           default.  Note that the assembler will always align instructions
1147           like "LOOP" that have fixed alignment requirements.
1148
1149       --longcalls | --no-longcalls
1150           Enable or disable transformation of call instructions to allow
1151           calls across a greater range of addresses.    This option should be
1152           used when call targets can potentially be out of range.  It may
1153           degrade both code size and performance, but the linker can
1154           generally optimize away the unnecessary overhead when a call ends
1155           up within range.  The default is --no-longcalls.
1156
1157       --transform | --no-transform
1158           Enable or disable all assembler transformations of Xtensa
1159           instructions, including both relaxation and optimization.  The
1160           default is --transform; --no-transform should only be used in the
1161           rare cases when the instructions must be exactly as specified in
1162           the assembly source.  Using --no-transform causes out of range
1163           instruction operands to be errors.
1164
1165       --rename-section oldname=newname
1166           Rename the oldname section to newname.  This option can be used
1167           multiple times to rename multiple sections.
1168
1169       The following options are available when as is configured for a Z80
1170       family processor.
1171
1172       -z80
1173           Assemble for Z80 processor.
1174
1175       -r800
1176           Assemble for R800 processor.
1177
1178       -ignore-undocumented-instructions
1179       -Wnud
1180           Assemble undocumented Z80 instructions that also work on R800
1181           without warning.
1182
1183       -ignore-unportable-instructions
1184       -Wnup
1185           Assemble all undocumented Z80 instructions without warning.
1186
1187       -warn-undocumented-instructions
1188       -Wud
1189           Issue a warning for undocumented Z80 instructions that also work on
1190           R800.
1191
1192       -warn-unportable-instructions
1193       -Wup
1194           Issue a warning for undocumented Z80 instructions that do not work
1195           on R800.
1196
1197       -forbid-undocumented-instructions
1198       -Fud
1199           Treat all undocumented instructions as errors.
1200
1201       -forbid-unportable-instructions
1202       -Fup
1203           Treat undocumented Z80 instructions that do not work on R800 as
1204           errors.
1205

SEE ALSO

1207       gcc(1), ld(1), and the Info entries for binutils and ld.
1208
1210       Copyright (c) 1991-2013 Free Software Foundation, Inc.
1211
1212       Permission is granted to copy, distribute and/or modify this document
1213       under the terms of the GNU Free Documentation License, Version 1.3 or
1214       any later version published by the Free Software Foundation; with no
1215       Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
1216       Texts.  A copy of the license is included in the section entitled "GNU
1217       Free Documentation License".
1218
1219
1220
1221binutils-2.24                     2019-02-02                             AS(1)
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