1GENLIB_LOSIG.3(October 1, 1997) GENLIB_LOSIG.3(October 1, 1997)
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6 GENLIB_LOSIG - declare an internal logical signal, or a vector of
7 internal logical signals
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10 #include <genlib.h>
11 void GENLIB_LOSIG(name)
12 char ∗name;
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15 name Name of a signal to be declared
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18 LOSIG creates the internal signal, or the set of internal signals cor‐
19 responding to a vector description, represented by name. See BUS(3)
20 and ELM(3) for more details on vectors.
21 The need for declaring signal is mostly felt when one wants to create a
22 consistent vector declaration, for file formats that do not allow par‐
23 tial or multiple declarations, like vhdl. This way, a user can create
24 a vector and access its member the way he wants, but still having an
25 internal consistent form.
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27 Warning If a signal is declared with LOSIG, but not used,
28 the resulting file will have an internal node
29 floating. This is not an error from a genlib point
30 of view, so the user must be aware of it.
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33 #include <genlib.h>
34 main()
35 {
36 /∗ Create a figure to work on ∗/
37 GENLIB_DEF_LOFIG("cell");
38 /∗ Define interface ∗
39 GENLIB_LOCON(...
40 /∗ declare buses ∗/
41 GENLIB_LOSIG("grum[23:0]");
42 GENLIB_LOSIG("iconection[0:7]");
43 /∗ Place an instance ∗/
44 GENLIB_LOINS("no2_y" ,"no3" ,"grum[12]" ,"a9_s" ,"new_no3_s" ,"vdd" ,"vss" ,0);
45 GENLIB_LOINS("no2_y" ,"no4" ,"a12_s" ,"grum[6]" ,"no4_s" ,"vdd" ,"vss" ,0);
46 GENLIB_LOINS("a2_y" ,"a22" ,"no3_s" ,"grum[15]" ,"a22_s" ,"vdd" ,"vss" ,0);
47 /∗ Save all that on disk ∗/
48 GENLIB_SAVE_LOFIG();
49 }
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52 genlib(1), GENLIB_LOINS(3), GENLIB_LOCON(3), GENLIB_BUS(3), GEN‐
53 LIB_ELM(3).
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60PROCEDURAL GENERATION LANGUAGE ASIM/LIP6 GENLIB_LOSIG.3(October 1, 1997)