1SigParser(3) User Contributed Perl Documentation SigParser(3)
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6 Verilog::SigParser - Signal Parsing for Verilog language files
7
9 use Verilog::Preproc;
10 use Verilog::SigParser;
11 my $pp = Verilog::Preproc->new(keep_comments=>0,);
13 my $parser = new Verilog::SigParser;
15 $parser->parse_preproc_file($pp);
16 # The below described callbacks are then invoked
17
19 Verilog::SigParser builds upon the Verilog::Parser module to provide
20 callbacks for when a signal is declared, a module instantiated, or a
21 module defined.
22 See the "Which Package" section of Verilog::Language if you are unsure
24 which parsing package to use for a new application. For a higher level
25 interface to this package, see Verilog::Netlist.
26
28 The method interface to Verilog::SigParser is described in the
29 Verilog::Parser module which this package inherits. You will probably
30 want to use the preprocessing option of Verilog::Parser with this
31 package.
32
34 In order to make the parser do anything interesting, you must make a
35 subclass where you override one or more of the following methods as
36 appropriate.
37 Note Verilog::Parser callbacks also are invoked when SigParser is
39 parsing.
40 $self->attribute($text)
42 Scanned an attribute or meta-comment. The parser inspects the
43 first word of each comment line ("//key rest" to end of line) or
44 comment block ("/*key rest */). It calls "$self-"attribute(
45 meta_text )" if the first word has a true value in hash
46 "$self-"metacomment>.
47 $self->class($token, $name, $virtual)
49 This method is called at a class.
50 $self->covergroup($token, $name)
52 This method is called at a covergroup.
53 $self->contassign($token, $lhs, $rhs)
55 This method is called at a continuous "assign" keyword, with the
56 left and right hand part of the assignment. Note that "wire"
57 initializations are not considered assignments; those are received
58 via the var callback's value parameter.
59 $self->defparam($token, $lhs, $rhs)
61 This method is called at a "defparam" keyword, with the left and
62 right hand part of the assignment.
63 $self->endcell($token)
65 This method is called at the end of defining a cell. It is useful
66 for writing clean up routines.
67 $self->endgroup($token)
69 This method is called at the end of defining a covergroup. It is
70 useful for writing clean up routines.
71 $self->endinterface($token)
73 This method is called at a endinterface keyword. It is useful for
74 writing clean up routines.
75 $self->endclass($token)
77 This method is called at a endclass keyword. It is useful for
78 writing clean up routines.
79 $self->endtaskfunc($token)
81 This method is called at a endfunction or endtask keyword. It is
82 useful for writing clean up routines.
83 $self->endmodport($token)
85 This method is called at a endmodport keyword. It is useful for
86 writing clean up routines.
87 $self->endmodule($token)
89 This method is called at a endmodule keyword. It is useful for
90 writing clean up routines.
91 $self->endpackage($token)
93 This method is called at a endpackage keyword. It is useful for
94 writing clean up routines.
95 $self->endprogram($token)
97 This method is called at a endprogram keyword. It is useful for
98 writing clean up routines.
99 $self->function($keyword, $name, $data-type)
101 This method is called when a function is defined. Type is the
102 output size or typename, plus "signed", for example "", "[3:0]",
103 "integer", or "signed [2:0]".
104 $self->import($package, $id)
106 This method is called when an import is defined.
107 $self->instant($module, $cell, $range)
109 This method is called when a instantiation is defined. The first
110 parameter is the name of the module being instantiated. The second
111 parameter is the name of the cell, which may be "" for primitives.
112 The third is the range if the cell was arrayed.
113 Prior to version 3.000, the name of the parameters were also
115 included in this callback. This has been replaced with the parampin
116 callback.
117 $self->interface($keyword, $name)
119 This method is called when an interface is defined.
120 $self->modport($keyword, $name)
122 This method is called when an interface modport is defined.
123 $self->module($keyword, $name, ignored, $in_celldefine)
125 This method is called when a module is defined.
126 $self->package($keyword, $name)
128 This method is called when a package is defined.
129 $self->parampin($name, $connection, $index)
131 This method is called when a parameter is connected to an
132 instantiation, IE the "#(...)" syntax. It is also used for UDP
133 delays (Three calls for "#(delay0,delay1,delay2)"), as the parser
134 does not know if the instantiation is for an UDP versus a module.
135 $self->pin($name, $connection, $index)
137 This method is called when a pin on an instant is defined and
138 "use_pinselects" is not set (the default, see pinselects() below.
139 If a pin name was not provided and the connection is by position,
140 name will be '' or undef.
141 If you do not need the pin nor var nor port callbacks, consider the
143 "$self->new (... use_vars=>0 ...)" option to accelerate parsing.
144 $self->pinselects($name, $connections, $index)
146 If "$self->new (... use_pinselects=>1 ...)" is used this function
147 is called instead of "$self->pin (...)". The difference is that
148 the second parameter ("$connections") is a Perl hash that contains
149 all connected nets in the case of concatenations including the MSB
150 and LSB bounds used at these locations.
151 $self->port($name, $objof, $direction, $data_type, $array, $pinnum)
153 This method is called when a module port is defined. It may be
154 called twice on a port if the 1995 style is used; the first call is
155 made at the port header, the second call at the input/output
156 declaration.
157 The first argument $name, is the name of the port. $objof is what
159 the port is an object of ('module', 'function', etc). $direction
160 is the port direction ('input', 'output', 'inout', 'ref', 'const
161 ref', or 'interface'). $data_type is the data type ('reg',
162 'user_type_t', 'signed [31:0]', etc, or for interfaces the
163 "{interface_id}.{modport_name}"). $array is the arraying of the
164 port ('[1:0][2:0]', '', etc). $pinnum is set to the pin number for
165 ANSI style declarations, and 0 for Verilog 1995 declarations made
166 outside the port list.
167 If you do not need the pin nor var nor port callbacks, consider the
169 "$self->new (... use_vars=>0 ...)" option to accelerate parsing.
170 $self->ppdefine($defvar, $definition)
172 This method is called when a preprocessor definition is
173 encountered.
174 $self->program($keyword, $name)
176 This method is called when a program is defined.
177 $self->signal_decl($keyword, $signame, $vector, $mem, $signed, $value)
179 This method is no longer used, see $self->var.
180 $self->task($keyword, $name)
182 This method is called when a task is defined.
183 $self->var($kwd, $name, $objof, $nettype, $data_type, $array, $value)
185 This method is called when a variable or net is defined.
186 The first argument $kwd is how it was declared ('port', 'var',
188 'genvar', 'parameter', 'localparam', 'typedef') or if applicable a
189 net type ('supply0', 'wire', etc). $name is the name of the
190 variable. $objof is what the variable is an object of ('module',
191 'function', etc). $nettype is the net type if any was defined ('',
192 'supply0', 'wire', 'tri', etc). $data_type is the data type
193 ('user_type_t', '[31:0] signed', etc). $array is the arraying of
194 the variable which is the text AFTER the variable name
195 ('[1:0][2:0]', '', etc). $value is what the variable was assigned
196 to ('', or expression).
197 Note typedefs are included here, because "parameter type" is both a
199 variable and a type declaration.
200 If you do not need the pin nor var nor port callbacks, consider the
202 "$self->new (... use_vars=>0 ...)" option to accelerate parsing.
203 Below are some example declarations and the callbacks:
205 reg [4:0] vect = 5'b10100;
207 # VAR 'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100'
208 wire (weak0, weak1) value = pullval;
209 # VAR 'net' 'value' 'module' 'wire' '' '' 'pullval'
210 reg [1:0] mem [12:2];
211 # VAR 'var' 'mem' 'module' '' 'reg [1:0]' '[12:2]' ''
212 int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
213 # verilog/parser_sv.v:121: VAR 'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}'
214 module ( output logic [SZ-1:0] o_sized );
215 # VAR 'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' ''
216 struct packed signed { bit [7:0] m_b; };
217 # VAR 'member' 'm_b' 'struct' '' 'bit [7:0]' '' ''
218
220 This is being distributed as a baseline for future contributions.
221 Don't expect a lot, the Parser is still naive, and there are many
222 awkward cases that aren't covered.
223 Note the SigParser is focused on extracting signal information. It
225 does NOT extract enough information to derive general interconnect; for
226 example the contents of 'assign' statements are not parsed.
227
229 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
230 software tool suite. The latest version is available from CPAN and
231 from <http://www.veripool.org/verilog-perl>.
232 Copyright 2000-2019 by Wilson Snyder. This package is free software;
234 you can redistribute it and/or modify it under the terms of either the
235 GNU Lesser General Public License Version 3 or the Perl Artistic
236 License Version 2.0.
237
239 Wilson Snyder <wsnyder@wsnyder.org>
240
242 Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist,
243 Verilog::Getopt
244perl v5.28.1 2019-05-04 SigParser(3)