1PROL(5) RDS FILE FORMATS PROL(5)
2
6 prol - define the rules for symbolic to real layout translation
7
9 This file describes the rules used by the mbk(1) to rds translator. In
10 the following file, symbolic layout objects are referred as mbk(1)
11 objects, mbk(1) being the internal data structure that supports sym‐
12 bolic representation. On the other hand, rds is a data structure
13 describing mainly rectangles, and is therefore used for real layout
14 representation.
15 Some syntaxic remarques on the way to write the file follow. The case
17 of identifiers is not significant, so NDIF is equivalent to NdiF. Com‐
18 ments are allowed anywhere in the file, using the sharp (#) as start of
19 comment, and newline as end of comment. A line beginning with a sharp
20 will be ignored, and a line containing a sharp will be read up to the
21 character preeceding it. A newline can be escaped using the backslash
22 ( followed by the newline. If some character, spaces or tabs for exam‐
23 ple, follow the backslash, chances are that a syntax error will be
24 issued.
25 First, some important process parameters are needed, the physical grid
27 step, that is the least common multiple of all the technologies values
28 in terms of layout distances, and the lambda, computed from a careful
29 observation of the process design rules.
30 Then, a set of tables is needed, to describe how to translate a sym‐
31 bolic object, belonging to the mbk(1) world, and a set of layout rec‐
32 tangles, in rds.
33 Each table has a special meaning, and its parametrization exend being
34 not full, some borders are to be evocated. Several type of table
35 exists indeed. Some are needed for object translation, others for post
36 treatment parametrization, others to define cif or gds identifiers
37 regarding rds ones.
38 Many things seem to be parametrizable, but in fact, mostly, if not
39 only, numbers, names in cif and gds translation tables, and boolean
40 value in post treatement may be changed without problems.
41 For any table, if some layer is not applicable, it can simply be omit‐
43 ted. The default action is `do nothing', or use a value of 0.0 for all
44 entries.
45
47 Since the goal of this file is to allow translation from mbk(1) to rds,
48 the meaning of the layers in both representation shall be known.
49 Mbk layers
50 NWELL minimum width 4 ; N-well.
52 PWELL minimum width 4 ; P-well.
54 NTIE minimum width 2 ; N diffusion for polarisa‐
56 tion.
57 PTIE minimum width 2 ; P diffusion for polarisa‐
59 tion.
60 NDIF minimum width 2 ; N diffusion for transistor.
62 PDIF minimum width 2 ; P diffusion for transistor.
64 NTRANS minimum width 1 (gate width) ; N transistor.
66 PTRANS minimum width 1 (gate width) ; P transistor.
68 POLY minimum width 1 ; polysilicon, not transistor
70 gate.
71 ALU1 minimum width 1 ; first level of metal.
73 ALU2 minimum width 2 ; second level of metal.
75 ALU3 minimum width 3 ; third level of metal
77 (unused).
78 TPOLY minimum width 1 ; through route for POLY.
80 TALU1 minimum width 1 ; through route for ALU1.
82 TALU2 minimum width 2 ; through route for ALU2.
84 TALU3 minimum width 3 ; through route for ALU3
86 (unused).
87 Mbk patterns
88 CONT_POLY cut pattern from ALU1 to POLY
90 CONT_VIA cut pattern from ALU1 to ALU2
92 CONT_VIA2 cut pattern from ALU2 to ALU3
94 CONT_DIF_N cut pattern from ALU1 to NDIF
96 CONT_DIF_P cut pattern from ALU1 to PDIF
98 CONT_BODY_N cut pattern from ALU1 to NTIE
100 CONT_BODY_P cut pattern from ALU1 to PTIE
102 C_X_N corner primitive for L or S shaped N transis‐
104 tor
105 C_X_P corner primitive for L or S shaped P transis‐
107 tor
108 Rds layers
109 RDS_NWELL N-well (or N-tub), bulk for P transistors.
111 RDS_PWELL P-well (or P-tub), bulk for N transistors.
113 RDS_NDIF use for symbolic extractor as equivalent of
115 NDIF.
116 RDS_PDIF use for symbolic extractor as equivalent of
118 PDIF.
119 RDS_NTIE use for symbolic extractor as equivalent of
121 NTIE.
122 RDS_PTIE use for symbolic extractor as equivalent of
124 PTIE.
125 RDS_POLY polysillicon run, for cell internal wirering.
127 RDS_GATE transistor polysillicon, for gate.
129 RDS_TPOLY polysillicon feed through. Indicate to a
131 router that a track is free of polysillicon.
132 RDS_CONT hole in the isolating layer between polysilli‐
134 con or active area and first metal level.
135 RDS_ALU1 first metal level run.
137 RDS_TALU1 first metal level feed through. Indicates to
139 a router that a track is free of first metal
140 level.
141 RDS_VIA1 hole in the isolating layer between first
143 metal level and second metal level.
144 RDS_ALU2 second metal level run.
146 RDS_TALU2 second metal level feed through. Indicate to
148 a router that a track is free of second metal
149 level.
150 RDS_VIA2 hole in the isolating layer between second
152 metal level and third metal level.
153 RDS_ALU3 third metal level run.
155 RDS_TALU3 third metal level feed through. Indicate to a
157 router that a track is free of third metal
158 level.
159 RDS_ALU4 fourth metal. (Used only for GaAs designs.)
161 RDS_VIA3 hole in the isolating layer between third
163 metal level and fourth metal level. (Used
164 only for GaAs designs.)
165 RDS_ACTIV active area dropped in N or P implant to build
167 transistors.
168 RDS_NIMP implant area, (sometime known as N select),
170 for N transistors.
171 RDS_PIMP implant area, (sometime known as P select),
173 for P transistors.
174 RDS_CPAS passivation, used in pads.
176 RDS_USER0 user defined purpose layer. (May be used for
178 DRC logical operations.)
179 RDS_USER1 user defined purpose layer. (May be used for
181 DRC logical operations.)
182 RDS_USER2 user defined purpose layer. (May be used for
184 DRC logical operations.)
185 RDS_REF virtual layer for the representation of sym‐
187 bolic references
188 RDS_ABOX virtual layer needed to indicate the abutment
190 box of a model.
191 RDS_DEFAULT default layer, shall never appear anywhere.
193
195 The following lines describe the file, entry by entry, specifying what
196 is expected.
197 Physical grid DEFINE PHYSICAL_GRID .5
199 This statement defines the minimum grid spacing
200 enforced by the foundry.
201 Lambda DEFINE LAMBDA 1
203 This defines the value of the lambda in microns.
204 This value, like any other one in the rest of the
205 file must be a multiple of the PHYSICAL_GRID.
206 Segment translation table
208 TABLE MBK_TO_RDS_SEGMENT
209 This table contains all the information needed to
210 translate a symbolic segment of a given layer onto
211 one, two or three real rectangles of specified lay‐
212 ers. An example of this table is given below, with
213 values needed for a technology where one lambda is
214 equal to 1.05 and the design grid is set to 0.15
215 microns.
216 TABLE MBK_TO_RDS_SEGMENT
218 NWELL RDS_NWELL VW 3.15 6.30 0.0 ALL
220 NDIF RDS_ACTIV VW 0.60 -0.90 0.0 ALL \
221 RDS_NIMP VW 2.10 2.10 0.0 ALL
222 PDIF RDS_ACTIV VW 0.60 -0.90 0.0 ALL \
223 RDS_PIMP VW 2.10 2.10 0.0 ALL
224 NTIE RDS_ACTIV VW 0.60 -0.90 0.0 ALL \
225 RDS_NIMP VW 1.20 0.30 0.0 ALL
226 PTIE RDS_ACTIV VW 0.60 -0.90 0.0 ALL \
227 RDS_PIMP VW 1.20 0.30 0.0 ALL
228 NTRANS RDS_GATE VW 0.00 0.15 0.0 ALL \
229 RDS_ACTIV VW -1.50 4.35 0.0 ALL \
230 RDS_NIMP VW 0.00 7.35 0.0 ALL
231 PTRANS RDS_GATE VW 0.00 0.15 0.0 ALL \
232 RDS_ACTIV VW -1.50 4.35 0.0 ALL \
233 RDS_PIMP VW 0.00 7.35 0.0 ALL
234 POLY RDS_POLY VW 0.60 0.15 0.0 ALL
235 ALU1 RDS_ALU1 VW 0.90 0.75 0.0 ALL
236 ALU2 RDS_ALU2 VW 0.90 -0.30 0.0 ALL
237 TPOLY RDS_TPOLY VW 0.60 0.15 0.0 ALL
238 TALU1 RDS_TALU1 VW 0.90 0.75 0.0 ALL
239 TALU2 RDS_TALU2 VW 0.90 -0.30 0.0 ALL
240 END
242 The first column is the mbk(1) layer name to be
244 translated, then there one or more groups of 6 col‐
245 umns each. For each physical rectangle, there are
246 3 parameters :
247 - rds layer name
248 - One of VW, LCW, RCW that indicates the `type' of
249 segment to be generated
250 - physical length extension: DLR
251 - physical width oversize: DWR
252 - offset from symbolic axis: OFFSET
253 - tools for which the generated rectangle is appli‐
254 cable: ALL, DRC (for the symbolic design rule
255 checker, see druc(1)), EXT (for the symbolic
256 extractor, see lynx(1)) These parameters are meant
257 regarding the symbolic segment.
258 Connectors translation table
260 TABLE MBK_TO_RDS_CONNECTOR
261 This table contains all the information needed to
262 translate a symbolic connector of a given layer
263 onto one single real rectangle.
264 An example of this table is given below, with val‐
265 ues needed for a technology where one lambda is
266 equal to 1.05 and the design grid is set to 0.15
267 micron.
268 TABLE MBK_TO_RDS_CONNECTOR
270 POLY RDS_POLY 0.6 0.15
272 ALU1 RDS_ALU1 0.9 0.75
273 ALU2 RDS_ALU2 0.9 -0.3
274 END
276 One symbolic connector is translated into one phys‐
277 ical rectangle using 3 parameters :
278 - rds layer name
279 - physical width oversize: DWR
280 - physical extension on each side of the abutment
281 box: DER
282 It is discouraged to use active or well layers as
284 connectors while designing.
285 Vias translation table
287 TABLE MBK_TO_RDS_VIA
288 This table contains all the information needed to
289 translate a symbolic via of a given layer onto one
290 to four real rectangles of user specified layers.
291 An example of this table is given below, with val‐
292 ues needed for a technology where one lambda is
293 equal to 1.05 and the design grid is set to 0.15
294 micron.
295 TABLE MBK_TO_RDS_VIA
297 CONT_BODY_N RDS_ALU1 3 RDS_CONT 1.5 RDS_ACTIV 3.3 RDS_NIMP 4.5
299 CONT_BODY_P RDS_ALU1 3 RDS_CONT 1.5 RDS_ACTIV 3.3 RDS_PIMP 4.5
300 CONT_DIF_N RDS_ALU1 3 RDS_CONT 1.5 RDS_ACTIV 3.3 RDS_NIMP 6.3
301 CONT_DIF_P RDS_ALU1 3 RDS_CONT 1.5 RDS_ACTIV 3.3 RDS_PIMP 6.3
302 CONT_POLY RDS_ALU1 3 RDS_CONT 1.5 RDS_POLY 3
303 CONT_VIA RDS_ALU1 3 RDS_VIA1 1.5 RDS_ALU2 3
304 CONT_VIA2
305 C_X_N RDS_GATE 1.2 RDS_ACTIV 5.4 RDS_NIMP 8.4
306 C_X_P RDS_GATE 1.2 RDS_ACTIV 5.4 RDS_PIMP 8.4
307 END
309 This table describes how to translate one symbolic
311 via, to 2, 3 or 4 physical rectangles. The table
312 is defined as follow : The first column is the
313 mbk(1) via name to translate, then there are 4
314 groups of 2 columns each, which correspond to four
315 potential targets rds rectangles of user specified
316 layer. In one group the first column is the rds
317 layer name, the second one is the rds layer width.
318 The rectangle is centered on the contact coordi‐
319 nates, and expands in the four direction of half
320 the given width value.
321 Denotching values table
323 TABLE S2R_OVERSIZE_DENOTCH
324 This table contains the oversize value needed to
325 erase notches. All the rectangles of the same rds
326 layer are oversized by this value and then merged
327 altogether and undersized by the same value. An
328 example of this table is given below.
329 TABLE S2R_OVERSIZE_DENOTCH
331 RDS_NWELL 3.00
333 RDS_POLY 0.75
334 RDS_GATE 0.75
335 RDS_ALU1 0.75
336 RDS_ALU2 0.75
337 RDS_ACTIV 1.05
338 RDS_NIMP 2.55
339 RDS_PIMP 2.55
340 END
342 For some rds layers, like RDS_NWELL, RDS_NIMP and
343 RDS_PIMP, two rectangles distant from less or equal
344 the minimun spacing design rule must be merged in a
345 single one. In this case, the oversize value is
346 equal to the minimum spacing rule between two edges
347 of the same layer divided by 2.
348 Some other rds layers, like RDS_ALU1, ..., must not
349 be merged. In this case, the oversize value is
350 equal to the minimum spacing rule between two edges
351 of the same layer divided by 2, minus the physical
352 grid.
353 Some layers never create notch, such as RDS_VIA1 or
354 RDS_CONT, so the oversize value is null.
355 Ring width TABLE S2R_BLOC_RING_WIDTH
357 s2r must merge segments to erase notches even if
358 those segments are in two different hierarchical
359 level blocs, for example, two blocs abuted side to
360 side. So, it must be able to fetch segments inside
361 blocs. It is not needed to flatten the entire
362 bloc, only a ring is necessary. The ring is com‐
363 puted from the abutment box edges or from the
364 envelop edges of the overlapping blocs.
365 An example of this table is given below.
366 TABLE S2R_BLOC_RING_WIDTH
368 RDS_NWELL 6
370 RDS_POLY 1.8
371 RDS_GATE 1.8
372 RDS_ALU1 1.8
373 RDS_ALU2 1.8
374 RDS_ACTIV 2.4
375 RDS_NIMP 1.8
376 RDS_PIMP 1.8
377 END
379 The normal ring width is the minimum spacing design
380 rule between two segments of the same rds layer.
381 A zero means that no ring is wanted for that rds
382 layer.
383 Minimum real layer width design rule
385 TABLE S2R_MINIMUM_LAYER_WIDTH
386 This table contains the minimum width of each rds
387 layer. It is used by s2r to avoid creating rectan‐
388 gles below the minimum required, during the merge
389 operation.
390 TABLE S2R_MINIMUM_LAYER_WIDTH
392 RDS_NWELL 6
393 RDS_POLY 1.2
394 RDS_GATE 1.2
395 RDS_ALU1 1.8
396 RDS_ALU2 1.8
397 RDS_ACTIV 1.2
398 RDS_NIMP 2.7
399 RDS_PIMP 2.7
400 END
402 A zero can be specified, when it is sure that this
403 layer is not to be merged, because not treated by
404 s2r.
405 Post treatment configuration table
407 TABLE S2R_POST_TREAT
408 This table indicates to s2r which rds layers must
409 be post-processed. Precicely if a layer is only to
410 be be translated, or translated and then post-pro‐
411 cessed. Translated means translate and fit from
412 symbolic to real, and postreated that it should
413 also be merged with its neighbours. For example,
414 it's not necessary to merge cut layers such as
415 RDS_CONT.
416 TABLE S2R_POST_TREAT
418 RDS_NWELL TREAT NULL
420 RDS_PWELL NOTREAT NULL
421 RDS_NDIF NOTREAT NULL
422 RDS_PDIF NOTREAT NULL
423 RDS_NTIE NOTREAT NULL
424 RDS_PTIE NOTREAT NULL
425 RDS_POLY TREAT NULL
426 RDS_GATE TREAT NULL
427 RDS_TPOLY NOTREAT NULL
428 RDS_CONT NOTREAT NULL
429 RDS_ALU1 TREAT NULL
430 RDS_TALU1 NOTREAT NULL
431 RDS_VIA1 NOTREAT NULL
432 RDS_ALU2 TREAT NULL
433 RDS_TALU2 NOTREAT NULL
434 RDS_VIA2 NOTREAT NULL
435 RDS_ALU3 NOTREAT NULL
436 RDS_TALU3 NOTREAT NULL
437 RDS_ACTIV TREAT NULL
438 RDS_NIMP TREAT RDS_PIMP
439 RDS_PIMP TREAT RDS_NIMP
440 RDS_REF NOTREAT NULL
441 RDS_ABOX NOTREAT NULL
442 END
444 If set to NOTREAT, the first parameter indicates a
445 translation. If set to TREAT, then the layer is
446 translated and then post-treated
447 To post-process creates problems with the implanta‐
448 tion layers. It is possible to have a good sym‐
449 bolic layout (no symbolic design rule errors), and
450 have a resulting layout with DRC violations, cre‐
451 ated by a poor post-processing. It is due to the
452 fact that these layers do not exist in symbolic, so
453 it is not possible to apply them drc verifications.
454 If two rectangles of these layers are too close
455 (less than a given value), they must be merged.
456 Generally, there is no problem, but when corners
457 are too near it is impossible to merge with the
458 classical algorithm, expand, merge, then shrink.
459 Rectangles, known as scotches, are created to merge
460 anyway, like this :
461 +--------+ +--------+ +-----+--+
463 |////////| |////////| |/////|//|
464 |//+--+//| |//+--+//| |//+--|//|
465 |//| |//| gives -> |//| |//| or -> |//| |//|
466 |//+--+//| +-----------+ |//+--|//|
467 |////////| |///////////| |/////|//|
468 +--------+ +--------+//| +-----|//|
469 ^ +--------+ |//|-----+ |//+--------+
470 | |////////| |//|/////| |///////////|
471 o--->|//+--+//| |//|--+//| +-----------+
472 | |//| |//| |//| |//| |//| |//|
473 implant |//+--+//| |//|--+//| |//|--+//|
474 areas |////////| |//|/////| |//|/////|
475 +--------+ +--+-----+ +--+-----+
476 A N implantation layer should not overlap a P
477 implantation one. We say that P implantations and
478 N implantations are complementary. A scotch will
479 not be created if it intersects with any of the
480 rectangles of the complementary layers.
481 If a record contains in the second field a rds
482 layer different from NULL, it indicates the comple‐
483 mentary layer. This implies that if it is a layer
484 that might need scotches the algorithm will try not
485 to intersect with it when creating scotches.
486 Extraction graph table
488 TABLE LYNX_GRAPH
489 This table gives the connexion graph between the
490 rds layers. For each layer, the list of the con‐
491 nectable layers is written. Up to now, the extrac‐
492 tor works only on translated symbolic layout.
493 TABLE LYNX_GRAPH
495 RDS_NDIF RDS_CONT RDS_NDIF
497 RDS_PDIF RDS_CONT RDS_PDIF
498 RDS_NTIE RDS_CONT RDS_NTIE
499 RDS_PTIE RDS_CONT RDS_PTIE
500 RDS_POLY RDS_CONT RDS_GATE RDS_POLY
501 RDS_GATE RDS_POLY RDS_GATE
502 RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT
503 RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF
504 RDS_REF RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF
505 RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1
506 RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2
507 RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2
508 RDS_ALU3 RDS_VIA2 RDS_ALU3
509 END
511 Extraction capacitance table
513 TABLE LYNX_CAPA
514 This table gives the capacitance in picofarad per
515 square lambda of each layer. The extractor com‐
516 putes only substrat capacitances. The capacitances
517 associated with gate or drain or sources are not
518 computed. On the other hand the transistor sizes
519 (area, perimeter) are computed. (This is to ensure
520 compatibility with Spice).
521 TABLE LYNX_CAPA
523 RDS_POLY 1.00e-04
525 RDS_ALU1 0.50e-04
526 RDS_ALU2 0.25e-04
527 END
529 Cif translation table
531 TABLE CIF_LAYER
532 This table gives the equivalence between internal
533 layers and their representation in the cif file
534 format. A table may look like that (for MOSIS lay‐
535 ers):
536 TABLE CIF_LAYER
538 RDS_NWELL CWN
540 RDS_PWELL CWP
541 RDS_ACTIV CAA
542 RDS_NIMP CSN
543 RDS_PIMP CSP
544 RDS_POLY CPG
545 RDS_GATE CPG
546 RDS_CONT CCA
547 RDS_ALU1 CMF
548 RDS_VIA1 CVA
549 RDS_ALU2 CMS
550 END
552 Gds translation table
554 TABLE GDS_LAYER
555 This table gives the equivalence between internal
556 layers and there representation in the gds file. A
557 table may look like that (for CMP layers):
558 TABLE GDS_LAYER
560 RDS_NWELL 1
562 RDS_POLY 11
563 RDS_GATE 11
564 RDS_CONT 16
565 RDS_ALU1 17
566 RDS_VIA1 18
567 RDS_ALU2 19
568 RDS_ACTIV 2
569 RDS_NIMP 12
570 RDS_PIMP 14
571 RDS_CPAS 20
572 END
574
576 Insights on the symbolic to real translation process are available in
577 the file mapping.ps
578ASIM/LIP6 October 1, 1997 PROL(5)