1ABC(1) User Commands ABC(1)
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6 abc - sequential logic synthesis and formal verification
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9 abc [OPTIONS] FILE
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12 ABC is a growing software system for synthesis and verification of
13 binary sequential logic circuits appearing in synchronous hardware
14 designs. ABC combines scalable logic optimization based on And-
15 Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for
16 look-up tables and standard cells, and innovative algorithms for
17 sequential synthesis and verification.
18 ABC provides an experimental implementation of these algorithms and a
20 programming environment for building similar applications. Future
21 development will focus on improving the algorithms and making most of
22 the packages stand-alone. This will allow the user to customize ABC
23 for their needs as if it were a toolbox rather than a complete tool.
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26 -c CMD Execute commands CMD.
27 -q CMD Execute commands CMD quietly.
29 -C CMD Execute commands CMD, then continue in interactive mode.
31 -F SCRIPT
33 Execute commands from script file SCRIPT and echo commands.
34 -f SCRIPT
36 Execute commands from script file SCRIPT.
37 -h Print command usage.
39 -o FILE
41 Store the result in FILE.
42 -s Do not read any initialization file.
44 -t TYPE
46 Specify the input type, one of blif_mv, blif_mvs, blif, or none.
47 The default is blif_mv.
48 -T TYPE
50 Specify the output type, one of blif_mv, blif_mvs, blif, or
51 none. The default is blif_mv.
52 -x Equivalent to -t none -T none.
54 -b Run in bridge mode.
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58 Data structures and algorithms at the heart of a software system deter‐
59 mine its capabilities in processing data and its efficiency as a pro‐
60 gramming environment for building new applications. Extensive experi‐
61 ence of developing and using SIS, VIS, and MVSIS, makes it clear that
62 these systems do not provide a flexible programming environment to
63 implement recent innovations, such as integration of technology mapping
64 and retiming. Specifically, the SIS environment is outdated and rather
65 inefficient when handling large circuits. VIS, designed as a formal
66 verification tool for multi-valued specifications, does not provide
67 enough flexibility for binary synthesis. MVSIS was developed and
68 extensively used by us in the recent years for implementing new synthe‐
69 sis algorithms for both multi-valued and binary networks. Finally, we
70 became convinced that (a) the basic data structures and algorithms of
71 MVSIS can be made considerably simpler and easier to use by assuming
72 binary networks, and (b) a central place in the new system should be
73 given to a new data structure, AIGs (multi-level logic networks com‐
74 posed of two-input ANDs and inverters), which promises improvements in
75 quality and runtime of synthesis and verification.
76 This understanding motivates us to redevelop the core packages of MVSIS
78 resulting in a new programming environment named ABC. As the name sug‐
79 gests, the primary goal is to keep data structures simple and flexible
80 for a wide range of applications. The “philosophy of ABC” has several
81 basic premises. One of them is allowing for a variety of functional
82 representations, such as BDDs and SOPs, to solve specialized tasks,
83 while defaulting to AIGs for the mainstream network manipulation. Rep‐
84 resenting logic using AIGs leads to a remarkable uniformity in computa‐
85 tion and efficient interfacing with CNF-based SAT solvers for handing
86 Boolean reasoning problems. Another fundamental premise of ABC is the
87 synergy between synthesis and verification using efficient SAT-based
88 Boolean reasoning on the AIG for combinational and sequential equiva‐
89 lence checking.
90 The goal of the ABC project is to provide a public-domain implementa‐
92 tion of the state-of-the-art combinational and sequential synthesis
93 algorithms and, at the same time, create an open-source environment, in
94 which such applications can be developed and compared. The current
95 version of ABC can optimize/map/retime industrial gate-level designs
96 with 100K gates and 10K sequential elements for optimal delay and
97 heuristically minimized area in about one minute of CPU time on a mod‐
98 ern computer. The runtime of the combinational synthesis, mapping, and
99 verification is typically faster.
100ABC 1.01 (20190608) ABC(1)