1VASY(1) CAO-VLSI Reference Manual VASY(1)
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6 VASY - VHDL Analyzer for Synthesis
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10 This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM
11 team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris,
12 France.
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14 Web : http://asim.lip6.fr/recherche/alliance/
15 E-mail : alliance-users@asim.lip6.fr
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18 vasy [-VpavsoipSHL] [-C num] [-E num] [-I format] [-P file] filename
19 [outname]
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22 VASY is a hierarchical VHDL Analyzer for Synthesis. VASY performs a
23 semantic analysis of a VHDL RTL description filename, with a VHDL sub‐
24 set much more extended than the Alliance one (see vasy(5) for more
25 details), and identifies with precision all the memorizing elements and
26 tristate buffers.
27 During its analysis, VASY expands generic parameters, executes generic
28 map and generate statements, and also unrolls static FOR loops.
29 At the end, VASY drives an equivalent description outname (in Verilog
30 or VHDL format) accepted by most of synthesis tools.
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34 MBK_WORK_LIB[24m(1)
35 indicates the path to the read/write directory for the ses‐
36 sion.
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40 -V Verbose mode on. Each step of the analysis is displayed on
41 the standard output.
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43 -v Drives an equivalent description in Verilog format.
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45 -a Drives an equivalent description in Alliance VHDL format
46 vbe(5) and/or vst(5). We can note that with this option, all
47 arithmetic operators are expanded in an equivalent set of
48 boolean expressions, because these operators don't belong to
49 the Alliance VHDL subset.
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51 -s Drives an equivalent VHDL description (with the extention
52 .vhd) accepted by most of industrial synthesis tools.
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54 -S Uses Std_logic instead of Bit (taken into account only with
55 option -s).
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57 -i Drives initial signal values (taken into account only with
58 option -s).
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60 -I format Specifies the VHDL input format such as Alliance VHDL format
61 vbe(5), vst(5) or industrial VHDL format vhd or vhdl.
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63 -H In a structural description, all model of instances are
64 recursively analyzed. (By default VASY analyzes only models
65 with generic parameters) The leaves cells are defined by a
66 file called CATAL (see catal(5) for details).
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68 -o Authorizes to overwrite existing files.
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70 -p Adds power supply connectors (vdd and vss). Useful option to
71 enter in Alliance.
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73 -C num When the size of the adder is greater or equal to num a Carry
74 Look Ahead adder is generated, instead of a Ripple Carry
75 adder. (taken into account only with option -a).
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77 -E num Comparators are expanded in an equivalent set of boolean
78 expressions, when their size is greater than num (taken into
79 account only with option -a).
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81 -L A file .lax (see lax(5) for details) is generated. This file
82 contains the list of all signals that must be kept during the
83 synthesis step, using boom (see boom(1) for details). (taken
84 into account only with option -a).
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86 -P file Specifies a 'file.pkg' containing a list of logical and phys‐
87 ical package name:
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89 work.constants.all : pkg_constants
90 work.components.all : pkg_components
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94 vasy(5), vbe(5), vhdl(5), catal(5). lax(5). asimut(1), boom(1),
95 MBK_WORK_LIB(1). MBK_CATA_LIB(1). MBK_CATAL_NAME(1).
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101ASIM/LIP6 November 26, 1999 VASY(1)