1YOSYS-SMTBMC(19 April 2020)                        YOSYS-SMTBMC(19 April 2020)
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NAME

6       yosys-smtbmc - write design to SMT2-LIBv2 file
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SYNOPSIS

9       yosys-smtbmc [options] <yosys_smt2_output>
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OPTIONS

13       -t [<skip_steps>:]<num_steps>
14              default: skip_steps=0, num_steps=20
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16       -u <start_step>
17              assume asserts in skipped steps in BMC
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19       -S <step_size>
20              proof <step_size> time steps at once
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22       -c <vcd_filename>
23              write  counter-example  to  this VCD file (hint: use 'write_smt2
24              -wires' for maximum coverage of signals in generated VCD file)
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26       -i     instead of BMC run temporal induction
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28       -m <module_name>
29              name of the top module
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31       -s <solver>
32              Set SMT solver: z3, cvc4, yices, mathsat. default: z3
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34       -v     enable debug output
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36       -p     disable timer display during solving
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38       -d <filename>
39              write smt2 statements to file
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AUTHOR

42       This manual page was written by Sebastian  Kuzminsky  <seb@highlab.com>
43       for the Debian project (and may be used by others).
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47                                                   YOSYS-SMTBMC(19 April 2020)
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