1RING(1) ALLIANCE USER COMMANDS RING(1)
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6 RING - PAD RING router
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9 RING source result [ stat ]
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13 This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM
14 team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris,
15 France.
16 Web : http://asim.lip6.fr/recherche/alliance/
18 E-mail : alliance-users@asim.lip6.fr
19
21 source defines two input files:
22 -- the file describing the input netlist (MBK_IN_LO(1) format).
23 example: source.al
24 -- the parameter file: source.rin
26 This file consists in 5 sections: 4 for the pad placement on
27 circuit sides, one to define the power sypply width (in lambda
28 units).
29 example:
31 east () # none pad at east side.
32 north (
33 p_pck p_i0 p_i1
34 p_i3)
35 south (p_vssb p_vddb p_i2)
36 width (vss 50 vdd 80)
37 Separators (spaces, tabulations and new line) are allowed
39 between instance names.
40 -- east(), north(), south(), west() define the relative pad
42 order. They use the pad instance names.
43 For the north() and south() sections, the instance name declara‐
45 tion are from the left (first pad) to the right (last pad).
46 For the east() and west() sections, the instance name declara‐
48 tion are from the bottom (first pad) to the top (last pad).
49 Any section may be missing. It means so the revalive side has no
51 pad, however at least one side must has one pad.
52 -- the width() section is optional and describes the power
54 (vdd), and ground (vss) track width.
55 result defines the output filename.
57 This file contains the layout of the routed circuit
59 (MBK_OUT_PH(1) format).
60 example: result.ap
61 RING uses a pad library whose path directory is defined with the
63 MBK_CATA_LIB(1) environment variable. It also uses a catalog
64 filename which is defined with the MBK_CATAL_NAME(1) environment
65 variable.
66 The catalog must contain all the pad model names used in the
67 circuit. The core model-name must not be present in the catalog.
68 Part of catalog file:
70 a2_y C
71 high_y C
72 pck_sp C
73 piot_sp C
74 pvssick_sp C
75 ...
76 pvdde_sp C
77 pvddi_sp C
78 [stat] (optional parameter) defines another output file:
80 -- the statistic file: result.stat
82 It contains data about length (lambdas) and area (lambdas *
84 lambdas) in ALU1 and ALU2, for each equipotential. It describes
85 how many vias were placed.
86 example: *** STATISTIC FILE < result.stat > ***
88 Equipotential list :
90 index| name |lgth A1|lgth A2|area A1|area A2| nb vias
92 _________________________________________________________
93 60 | vss | 9034 | 4408 | 614288| 454024| 1128
94 _________________________________________________________
95 59 | vdd | 7494 | 3968 | 574248| 408704| 1128
96 _________________________________________________________
97 54 | b2_coeur | 2253 | 1899 | 2253| 3798| 4
98 _________________________________________________________
99 Total length alu1 : 18781 (lambdas)
100 Total length alu2 : 10275 (lambdas)
101 Total area alu1 : 1190789 (lambdas * lambdas)
102 Total area alu2 : 866526 (lambdas * lambdas)
103 Total of vias : 2260
104
106 MBK_IN_LO(1) defines the input file format for the netlist.
107 MBK_IN_PH(1) defines the input file format for the layout.
108 MBK_OUT_PH(1) defines the output file format for the layout.
109 MBK_CATAL_NAME(1) defines the catalog filename.
110 MBK_CATA_LIB(1) defines the library pad cells directory.
111 MBK_WORK_LIB(1) defines the work directory.
112
114 RING performs the physical routing between core of circuit and pad
115 ring. RING is not a floor plan router and allows only one core.
116 A core is designed, for example, with the standard cells placer ocp(1)
118 and router nero(1), which places the input and output connectors on the
119 abutment box. The physical core connectors must be separated by more
120 than one pitch in any metal (in ALU1 or ALU2).
121 Netlist and layout views relative to the same figure must have the same
123 name. For example, the netlist core name and the routed core name.
124 RING performs an automatic placement of the pad ring and core. It is
126 not necessary to place pads, but only to describe their relative posi‐
127 tion on each side, in the parameter file (source.rin).
128 Distance between the first track and any instance (pad or core) is the
130 pitch so 5 lambdas.
131
133 Let chip.al be the circuit netlist and core.ap the routed core. 80
134 lambdas for supply track width and the pad placement are described as
135 follows.
136 chip.rin:
138 # This is a comment: 1 comment per line
140 north(p_a1 p_a2 p_a3 p_a4)
141 south(
142 p_i1 #another comment: the rest of the line
143 p_i2
144 p_i3
145 p_i4)
146 east(p_b4 p_b3 p_b2 p_b1)
147 west(p_f1 p_f2 p_f3 p_f4)
148 width(
149 vdd 80
150 vss 80
151 )
152 We want a ring of pads as follow:
154 +-------------------------------------------------+
156 | |p_a1|p_a2|p_a3|p_a4| |
157 |----+---------------------------------------+----|
158 |p_f4| |p_b1|
159 |----| +-------+ |----|
160 |p_f3| | | |p_b2|
161 |----| | CORE | |----|
162 |p_f2| | | |p_b3|
163 |----| +-------+ |----|
164 |p_f1| |p_b4|
165 |----+---------------------------------------+----|
166 | |p_i1|p_i2|p_i3|p_i4| |
167 +-------------------------------------------------+
168 In order to obtain the routed circuit (chipr.ap):
170 > ring chip chipr
172
174 genlib(1) lvx(1) ocp(1) nero(1) druc(1)
175
179 Physical core must have at least one physical connector by side, other‐
180 wise it can't place pads correctly, and maybe dump a core file.
181 Whenever lots of core connectors (bus) are placed close ones from each
183 others, RING may have problems to connect pad connectors placed just in
184 front of them. In such a case, it is recommended to not have pad con‐
185 nectors at that place and thus to place an instance pad without connec‐
186 tor (as pvdde_sp) or to cut the bus into several parts to let space
187 between connectors.
188 When core connectors are to close from corners, RING sometimes connects
190 those one to supply rings, to solve this bug, move core connectors or
191 change pad placement. In any case, use druc(1) or lvx(1) to detect
192 problem.
193 Supply vdd and vss pads (resp. pvddi_sp and pvssi_sp) must be placed as
195 close as possible of the core side middle (i.e. not in the corners).
196 Otherwise, RING cannot link supply pad connector to ring supplies and
197 exits with a error message.
198 Supply tracks from pads and core are connected at the supply ring.
200 There is sometimes few problems when core and pad tracks are opposite.
201 Move pads usually corrects problem.
202ASIM/LIP6 October 1, 1997 RING(1)