1HCT::lang::hdl::verilogU(s3e)r Contributed Perl DocumentaHtCiTo:n:lang::hdl::verilog(3)
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NAME

6       HCT::lang::hdl::verilog - Class of Verilog language.
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DESCRIPTION

9       Verilog is a hardware description language (HDL) used to model
10       electronic systems. Verilog HDL, not to be confused with VHDL, is most
11       commonly used in the design, verification, and implementation of
12       digital logic chips at the Register transfer level (RTL) level of
13       abstraction. It is also used in the verification of analog and mixed-
14       signal circuits.
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VERILOG SYNTAX

17       A description of the syntax in Backus-Naur form (predates the IEEE-1364
18       standard): <http://www.verilog.com/VerilogBNF.html>. Also a heavily
19       linked BNF syntax for Verilog 2001 can be found here
20       <http://www.externsoft.ch/download/verilog.html>.
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24perl v5.32.0                      2020-07-28        HCT::lang::hdl::verilog(3)
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