1AS(1)                        GNU Development Tools                       AS(1)
2
3
4

NAME

6       AS - the portable GNU assembler.
7

SYNOPSIS

9       as [-a[cdghlns][=file]] [--alternate] [-D]
10        [--compress-debug-sections]  [--nocompress-debug-sections]
11        [--debug-prefix-map old=new]
12        [--defsym sym=val] [-f] [-g] [--gstabs]
13        [--gstabs+] [--gdwarf-<N>] [--gdwarf-sections]
14        [--gdwarf-cie-version=VERSION]
15        [--help] [-I dir] [-J]
16        [-K] [-L] [--listing-lhs-width=NUM]
17        [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
18        [--listing-cont-lines=NUM] [--keep-locals]
19        [--no-pad-sections]
20        [-o objfile] [-R]
21        [--hash-size=NUM] [--reduce-memory-overheads]
22        [--statistics]
23        [-v] [-version] [--version]
24        [-W] [--warn] [--fatal-warnings] [-w] [-x]
25        [-Z] [@FILE]
26        [--sectname-subst] [--size-check=[error|warning]]
27        [--elf-stt-common=[no|yes]]
28        [--generate-missing-build-notes=[no|yes]]
29        [--target-help] [target-options]
30        [--|files ...]
31

TARGET

33       Target AArch64 options:
34          [-EB|-EL]
35          [-mabi=ABI]
36
37       Target Alpha options:
38          [-mcpu]
39          [-mdebug | -no-mdebug]
40          [-replace | -noreplace]
41          [-relax] [-g] [-Gsize]
42          [-F] [-32addr]
43
44       Target ARC options:
45          [-mcpu=cpu]
46          [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
47          [-mcode-density]
48          [-mrelax]
49          [-EB|-EL]
50
51       Target ARM options:
52          [-mcpu=processor[+extension...]]
53          [-march=architecture[+extension...]]
54          [-mfpu=floating-point-format]
55          [-mfloat-abi=abi]
56          [-meabi=ver]
57          [-mthumb]
58          [-EB|-EL]
59          [-mapcs-32|-mapcs-26|-mapcs-float|
60           -mapcs-reentrant]
61          [-mthumb-interwork] [-k]
62
63       Target Blackfin options:
64          [-mcpu=processor[-sirevision]]
65          [-mfdpic]
66          [-mno-fdpic]
67          [-mnopic]
68
69       Target BPF options:
70          [-EL] [-EB]
71
72       Target CRIS options:
73          [--underscore | --no-underscore]
74          [--pic] [-N]
75          [--emulation=criself | --emulation=crisaout]
76          [--march=v0_v10 | --march=v10 | --march=v32 |
77       --march=common_v10_v32]
78
79       Target C-SKY options:
80          [-march=arch] [-mcpu=cpu]
81          [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
82          [-fpic] [-pic]
83          [-mljump] [-mno-ljump]
84          [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
85          [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
86          [-mnolrw ] [-mno-lrw]
87          [-melrw] [-mno-elrw]
88          [-mlaf ] [-mliterals-after-func]
89          [-mno-laf] [-mno-literals-after-func]
90          [-mlabr] [-mliterals-after-br]
91          [-mno-labr] [-mnoliterals-after-br]
92          [-mistack] [-mno-istack]
93          [-mhard-float] [-mmp] [-mcp] [-mcache]
94          [-msecurity] [-mtrust]
95          [-mdsp] [-medsp] [-mvdsp]
96
97       Target D10V options:
98          [-O]
99
100       Target D30V options:
101          [-O|-n|-N]
102
103       Target EPIPHANY options:
104          [-mepiphany|-mepiphany16]
105
106       Target H8/300 options:
107          [-h-tick-hex]
108
109       Target i386 options:
110          [--32|--x32|--64] [-n]
111          [-march=CPU[+EXTENSION...]] [-mtune=CPU]
112
113       Target IA-64 options:
114          [-mconstant-gp|-mauto-pic]
115          [-milp32|-milp64|-mlp64|-mp64]
116          [-mle|mbe]
117          [-mtune=itanium1|-mtune=itanium2]
118          [-munwind-check=warning|-munwind-check=error]
119          [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
120          [-x|-xexplicit] [-xauto] [-xdebug]
121
122       Target IP2K options:
123          [-mip2022|-mip2022ext]
124
125       Target M32C options:
126          [-m32c|-m16c] [-relax] [-h-tick-hex]
127
128       Target M32R options:
129          [--m32rx|--[no-]warn-explicit-parallel-conflicts|
130          --W[n]p]
131
132       Target M680X0 options:
133          [-l] [-m68000|-m68010|-m68020|...]
134
135       Target M68HC11 options:
136          [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
137          [-mshort|-mlong]
138          [-mshort-double|-mlong-double]
139          [--force-long-branches] [--short-branches]
140          [--strict-direct-mode] [--print-insn-syntax]
141          [--print-opcodes] [--generate-example]
142
143       Target MCORE options:
144          [-jsri2bsr] [-sifilter] [-relax]
145          [-mcpu=[210|340]]
146
147       Target Meta options:
148          [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
149
150       Target MIPS options:
151          [-nocpp] [-EL] [-EB] [-O[optimization level]]
152          [-g[debug level]] [-G num] [-KPIC] [-call_shared]
153          [-non_shared] [-xgot [-mvxworks-pic]
154          [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
155          [-mfp64] [-mgp64] [-mfpxx]
156          [-modd-spreg] [-mno-odd-spreg]
157          [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
158          [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
159          [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
160          [-mips64r3] [-mips64r5] [-mips64r6]
161          [-construct-floats] [-no-construct-floats]
162          [-mignore-branch-isa] [-mno-ignore-branch-isa]
163          [-mnan=encoding]
164          [-trap] [-no-break] [-break] [-no-trap]
165          [-mips16] [-no-mips16]
166          [-mmips16e2] [-mno-mips16e2]
167          [-mmicromips] [-mno-micromips]
168          [-msmartmips] [-mno-smartmips]
169          [-mips3d] [-no-mips3d]
170          [-mdmx] [-no-mdmx]
171          [-mdsp] [-mno-dsp]
172          [-mdspr2] [-mno-dspr2]
173          [-mdspr3] [-mno-dspr3]
174          [-mmsa] [-mno-msa]
175          [-mxpa] [-mno-xpa]
176          [-mmt] [-mno-mt]
177          [-mmcu] [-mno-mcu]
178          [-mcrc] [-mno-crc]
179          [-mginv] [-mno-ginv]
180          [-mloongson-mmi] [-mno-loongson-mmi]
181          [-mloongson-cam] [-mno-loongson-cam]
182          [-mloongson-ext] [-mno-loongson-ext]
183          [-mloongson-ext2] [-mno-loongson-ext2]
184          [-minsn32] [-mno-insn32]
185          [-mfix7000] [-mno-fix7000]
186          [-mfix-rm7000] [-mno-fix-rm7000]
187          [-mfix-vr4120] [-mno-fix-vr4120]
188          [-mfix-vr4130] [-mno-fix-vr4130]
189          [-mfix-r5900] [-mno-fix-r5900]
190          [-mdebug] [-no-mdebug]
191          [-mpdr] [-mno-pdr]
192
193       Target MMIX options:
194          [--fixed-special-register-names] [--globalize-symbols]
195          [--gnu-syntax] [--relax] [--no-predefined-symbols]
196          [--no-expand] [--no-merge-gregs] [-x]
197          [--linker-allocated-gregs]
198
199       Target Nios II options:
200          [-relax-all] [-relax-section] [-no-relax]
201          [-EB] [-EL]
202
203       Target NDS32 options:
204           [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
205           [-misa=isa] [-mabi=abi] [-mall-ext]
206           [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
207           [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
208           [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
209           [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
210           [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
211           [-mb2bb]
212
213       Target PDP11 options:
214          [-mpic|-mno-pic] [-mall] [-mno-extensions]
215          [-mextension|-mno-extension]
216          [-mcpu] [-mmachine]
217
218       Target picoJava options:
219          [-mb|-me]
220
221       Target PowerPC options:
222          [-a32|-a64]
223          [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
224           -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
225           -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
226           -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
227           -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
228           -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
229          [-many] [-maltivec|-mvsx|-mhtm|-mvle]
230          [-mregnames|-mno-regnames]
231          [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
232          [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
233          [-msolaris|-mno-solaris]
234          [-nops=count]
235
236       Target PRU options:
237          [-link-relax]
238          [-mnolink-relax]
239          [-mno-warn-regname-label]
240
241       Target RISC-V options:
242          [-fpic|-fPIC|-fno-pic]
243          [-march=ISA]
244          [-mabi=ABI]
245
246       Target RL78 options:
247          [-mg10]
248          [-m32bit-doubles|-m64bit-doubles]
249
250       Target RX options:
251          [-mlittle-endian|-mbig-endian]
252          [-m32bit-doubles|-m64bit-doubles]
253          [-muse-conventional-section-names]
254          [-msmall-data-limit]
255          [-mpid]
256          [-mrelax]
257          [-mint-register=number]
258          [-mgcc-abi|-mrx-abi]
259
260       Target s390 options:
261          [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
262          [-mregnames|-mno-regnames]
263          [-mwarn-areg-zero]
264
265       Target SCORE options:
266          [-EB][-EL][-FIXDD][-NWARN]
267          [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
268          [-march=score7][-march=score3]
269          [-USE_R1][-KPIC][-O0][-G num][-V]
270
271       Target SPARC options:
272          [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
273           -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
274           -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
275           -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
276           -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
277           -Asparcvisr|-Asparc5]
278          [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
279           -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
280           -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
281           -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
282           -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
283           -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
284           -bump]
285          [-32|-64]
286          [--enforce-aligned-data][--dcti-couples-detect]
287
288       Target TIC54X options:
289        [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
290        [-merrors-to-file <filename>|-me <filename>]
291
292       Target TIC6X options:
293          [-march=arch] [-mbig-endian|-mlittle-endian]
294          [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
295          [-mpic|-mno-pic]
296
297       Target TILE-Gx options:
298          [-m32|-m64][-EB][-EL]
299
300       Target Visium options:
301          [-mtune=arch]
302
303       Target Xtensa options:
304        [--[no-]text-section-literals] [--[no-]auto-litpools]
305        [--[no-]absolute-literals]
306        [--[no-]target-align] [--[no-]longcalls]
307        [--[no-]transform]
308        [--rename-section oldname=newname]
309        [--[no-]trampolines]
310        [--abi-windowed|--abi-call0]
311
312       Target Z80 options:
313         [-march=CPU[-EXT][+EXT]]
314         [-local-prefix=PREFIX]
315         [-colonless]
316         [-sdcc]
317         [-fp-s=FORMAT]
318         [-fp-d=FORMAT]
319

DESCRIPTION

321       GNU as is really a family of assemblers.  If you use (or have used) the
322       GNU assembler on one architecture, you should find a fairly similar
323       environment when you use it on another architecture.  Each version has
324       much in common with the others, including object file formats, most
325       assembler directives (often called pseudo-ops) and assembler syntax.
326
327       as is primarily intended to assemble the output of the GNU C compiler
328       "gcc" for use by the linker "ld".  Nevertheless, we've tried to make as
329       assemble correctly everything that other assemblers for the same
330       machine would assemble.  Any exceptions are documented explicitly.
331       This doesn't mean as always uses the same syntax as another assembler
332       for the same architecture; for example, we know of several incompatible
333       versions of 680x0 assembly language syntax.
334
335       Each time you run as it assembles exactly one source program.  The
336       source program is made up of one or more files.  (The standard input is
337       also a file.)
338
339       You give as a command line that has zero or more input file names.  The
340       input files are read (from left file name to right).  A command-line
341       argument (in any position) that has no special meaning is taken to be
342       an input file name.
343
344       If you give as no file names it attempts to read one input file from
345       the as standard input, which is normally your terminal.  You may have
346       to type ctl-D to tell as there is no more program to assemble.
347
348       Use -- if you need to explicitly name the standard input file in your
349       command line.
350
351       If the source is empty, as produces a small, empty object file.
352
353       as may write warnings and error messages to the standard error file
354       (usually your terminal).  This should not happen when  a compiler runs
355       as automatically.  Warnings report an assumption made so that as could
356       keep assembling a flawed program; errors report a grave problem that
357       stops the assembly.
358
359       If you are invoking as via the GNU C compiler, you can use the -Wa
360       option to pass arguments through to the assembler.  The assembler
361       arguments must be separated from each other (and the -Wa) by commas.
362       For example:
363
364               gcc -c -g -O -Wa,-alh,-L file.c
365
366       This passes two options to the assembler: -alh (emit a listing to
367       standard output with high-level and assembly source) and -L (retain
368       local symbols in the symbol table).
369
370       Usually you do not need to use this -Wa mechanism, since many compiler
371       command-line options are automatically passed to the assembler by the
372       compiler.  (You can call the GNU compiler driver with the -v option to
373       see precisely what options it passes to each compilation pass,
374       including the assembler.)
375

OPTIONS

377       @file
378           Read command-line options from file.  The options read are inserted
379           in place of the original @file option.  If file does not exist, or
380           cannot be read, then the option will be treated literally, and not
381           removed.
382
383           Options in file are separated by whitespace.  A whitespace
384           character may be included in an option by surrounding the entire
385           option in either single or double quotes.  Any character (including
386           a backslash) may be included by prefixing the character to be
387           included with a backslash.  The file may itself contain additional
388           @file options; any such options will be processed recursively.
389
390       -a[cdghlmns]
391           Turn on listings, in any of a variety of ways:
392
393           -ac omit false conditionals
394
395           -ad omit debugging directives
396
397           -ag include general information, like as version and options passed
398
399           -ah include high-level source
400
401           -al include assembly
402
403           -am include macro expansions
404
405           -an omit forms processing
406
407           -as include symbols
408
409           =file
410               set the name of the listing file
411
412           You may combine these options; for example, use -aln for assembly
413           listing without forms processing.  The =file option, if used, must
414           be the last one.  By itself, -a defaults to -ahls.
415
416       --alternate
417           Begin in alternate macro mode.
418
419       --compress-debug-sections
420           Compress DWARF debug sections using zlib with SHF_COMPRESSED from
421           the ELF ABI.  The resulting object file may not be compatible with
422           older linkers and object file utilities.  Note if compression would
423           make a given section larger then it is not compressed.
424
425       --compress-debug-sections=none
426       --compress-debug-sections=zlib
427       --compress-debug-sections=zlib-gnu
428       --compress-debug-sections=zlib-gabi
429           These options control how DWARF debug sections are compressed.
430           --compress-debug-sections=none is equivalent to
431           --nocompress-debug-sections.  --compress-debug-sections=zlib and
432           --compress-debug-sections=zlib-gabi are equivalent to
433           --compress-debug-sections.  --compress-debug-sections=zlib-gnu
434           compresses DWARF debug sections using zlib.  The debug sections are
435           renamed to begin with .zdebug.  Note if compression would make a
436           given section larger then it is not compressed nor renamed.
437
438       --nocompress-debug-sections
439           Do not compress DWARF debug sections.  This is usually the default
440           for all targets except the x86/x86_64, but a configure time option
441           can be used to override this.
442
443       -D  Ignored.  This option is accepted for script compatibility with
444           calls to other assemblers.
445
446       --debug-prefix-map old=new
447           When assembling files in directory old, record debugging
448           information describing them as in new instead.
449
450       --defsym sym=value
451           Define the symbol sym to be value before assembling the input file.
452           value must be an integer constant.  As in C, a leading 0x indicates
453           a hexadecimal value, and a leading 0 indicates an octal value.  The
454           value of the symbol can be overridden inside a source file via the
455           use of a ".set" pseudo-op.
456
457       -f  "fast"---skip whitespace and comment preprocessing (assume source
458           is compiler output).
459
460       -g
461       --gen-debug
462           Generate debugging information for each assembler source line using
463           whichever debug format is preferred by the target.  This currently
464           means either STABS, ECOFF or DWARF2.  When the debug format is
465           DWARF then a ".debug_info" and ".debug_line" section is only
466           emitted when the assembly file doesn't generate one itself.
467
468       --gstabs
469           Generate stabs debugging information for each assembler line.  This
470           may help debugging assembler code, if the debugger can handle it.
471
472       --gstabs+
473           Generate stabs debugging information for each assembler line, with
474           GNU extensions that probably only gdb can handle, and that could
475           make other debuggers crash or refuse to read your program.  This
476           may help debugging assembler code.  Currently the only GNU
477           extension is the location of the current working directory at
478           assembling time.
479
480       --gdwarf-2
481           Generate DWARF2 debugging information for each assembler line.
482           This may help debugging assembler code, if the debugger can handle
483           it.  Note---this option is only supported by some targets, not all
484           of them.
485
486       --gdwarf-3
487           This option is the same as the --gdwarf-2 option, except that it
488           allows for the possibility of the generation of extra debug
489           information as per version 3 of the DWARF specification.  Note -
490           enabling this option does not guarantee the generation of any extra
491           infortmation, the choice to do so is on a per target basis.
492
493       --gdwarf-4
494           This option is the same as the --gdwarf-2 option, except that it
495           allows for the possibility of the generation of extra debug
496           information as per version 4 of the DWARF specification.  Note -
497           enabling this option does not guarantee the generation of any extra
498           infortmation, the choice to do so is on a per target basis.
499
500       --gdwarf-5
501           This option is the same as the --gdwarf-2 option, except that it
502           allows for the possibility of the generation of extra debug
503           information as per version 5 of the DWARF specification.  Note -
504           enabling this option does not guarantee the generation of any extra
505           infortmation, the choice to do so is on a per target basis.
506
507       --gdwarf-sections
508           Instead of creating a .debug_line section, create a series of
509           .debug_line.foo sections where foo is the name of the corresponding
510           code section.  For example a code section called .text.func will
511           have its dwarf line number information placed into a section called
512           .debug_line.text.func.  If the code section is just called .text
513           then debug line section will still be called just .debug_line
514           without any suffix.
515
516       --gdwarf-cie-version=version
517           Control which version of DWARF Common Information Entries (CIEs)
518           are produced.  When this flag is not specificed the default is
519           version 1, though some targets can modify this default.  Other
520           possible values for version are 3 or 4.
521
522       --size-check=error
523       --size-check=warning
524           Issue an error or warning for invalid ELF .size directive.
525
526       --elf-stt-common=no
527       --elf-stt-common=yes
528           These options control whether the ELF assembler should generate
529           common symbols with the "STT_COMMON" type.  The default can be
530           controlled by a configure option --enable-elf-stt-common.
531
532       --generate-missing-build-notes=yes
533       --generate-missing-build-notes=no
534           These options control whether the ELF assembler should generate GNU
535           Build attribute notes if none are present in the input sources.
536           The default can be controlled by the --enable-generate-build-notes
537           configure option.
538
539       --help
540           Print a summary of the command-line options and exit.
541
542       --target-help
543           Print a summary of all target specific options and exit.
544
545       -I dir
546           Add directory dir to the search list for ".include" directives.
547
548       -J  Don't warn about signed overflow.
549
550       -K  Issue warnings when difference tables altered for long
551           displacements.
552
553       -L
554       --keep-locals
555           Keep (in the symbol table) local symbols.  These symbols start with
556           system-specific local label prefixes, typically .L for ELF systems
557           or L for traditional a.out systems.
558
559       --listing-lhs-width=number
560           Set the maximum width, in words, of the output data column for an
561           assembler listing to number.
562
563       --listing-lhs-width2=number
564           Set the maximum width, in words, of the output data column for
565           continuation lines in an assembler listing to number.
566
567       --listing-rhs-width=number
568           Set the maximum width of an input source line, as displayed in a
569           listing, to number bytes.
570
571       --listing-cont-lines=number
572           Set the maximum number of lines printed in a listing for a single
573           line of input to number + 1.
574
575       --no-pad-sections
576           Stop the assembler for padding the ends of output sections to the
577           alignment of that section.  The default is to pad the sections, but
578           this can waste space which might be needed on targets which have
579           tight memory constraints.
580
581       -o objfile
582           Name the object-file output from as objfile.
583
584       -R  Fold the data section into the text section.
585
586       --hash-size=number
587           Set the default size of GAS's hash tables to a prime number close
588           to number.  Increasing this value can reduce the length of time it
589           takes the assembler to perform its tasks, at the expense of
590           increasing the assembler's memory requirements.  Similarly reducing
591           this value can reduce the memory requirements at the expense of
592           speed.
593
594       --reduce-memory-overheads
595           This option reduces GAS's memory requirements, at the expense of
596           making the assembly processes slower.  Currently this switch is a
597           synonym for --hash-size=4051, but in the future it may have other
598           effects as well.
599
600       --sectname-subst
601           Honor substitution sequences in section names.
602
603       --statistics
604           Print the maximum space (in bytes) and total time (in seconds) used
605           by assembly.
606
607       --strip-local-absolute
608           Remove local absolute symbols from the outgoing symbol table.
609
610       -v
611       -version
612           Print the as version.
613
614       --version
615           Print the as version and exit.
616
617       -W
618       --no-warn
619           Suppress warning messages.
620
621       --fatal-warnings
622           Treat warnings as errors.
623
624       --warn
625           Don't suppress warning messages or treat them as errors.
626
627       -w  Ignored.
628
629       -x  Ignored.
630
631       -Z  Generate an object file even after errors.
632
633       -- | files ...
634           Standard input, or source files to assemble.
635
636       The following options are available when as is configured for the
637       64-bit mode of the ARM Architecture (AArch64).
638
639       -EB This option specifies that the output generated by the assembler
640           should be marked as being encoded for a big-endian processor.
641
642       -EL This option specifies that the output generated by the assembler
643           should be marked as being encoded for a little-endian processor.
644
645       -mabi=abi
646           Specify which ABI the source code uses.  The recognized arguments
647           are: "ilp32" and "lp64", which decides the generated object file in
648           ELF32 and ELF64 format respectively.  The default is "lp64".
649
650       -mcpu=processor[+extension...]
651           This option specifies the target processor.  The assembler will
652           issue an error message if an attempt is made to assemble an
653           instruction which will not execute on the target processor.  The
654           following processor names are recognized: "cortex-a34",
655           "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
656           "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73",
657           "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "ares",
658           "exynos-m1", "falkor", "neoverse-n1", "neoverse-n2", "neoverse-v1",
659           "neoverse-e1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1"
660           and "xgene2".  The special name "all" may be used to allow the
661           assembler to accept instructions valid for any supported processor,
662           including all optional extensions.
663
664           In addition to the basic instruction set, the assembler can be told
665           to accept, or restrict, various extension mnemonics that extend the
666           processor.
667
668           If some implementations of a particular processor can have an
669           extension, then then those extensions are automatically enabled.
670           Consequently, you will not normally have to specify any additional
671           extensions.
672
673       -march=architecture[+extension...]
674           This option specifies the target architecture.  The assembler will
675           issue an error message if an attempt is made to assemble an
676           instruction which will not execute on the target architecture.  The
677           following architecture names are recognized: "armv8-a",
678           "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a", and
679           "armv8.6-a".
680
681           If both -mcpu and -march are specified, the assembler will use the
682           setting for -mcpu.  If neither are specified, the assembler will
683           default to -mcpu=all.
684
685           The architecture option can be extended with the same instruction
686           set extension options as the -mcpu option.  Unlike -mcpu,
687           extensions are not always enabled by default,
688
689       -mverbose-error
690           This option enables verbose error messages for AArch64 gas.  This
691           option is enabled by default.
692
693       -mno-verbose-error
694           This option disables verbose error messages in AArch64 gas.
695
696       The following options are available when as is configured for an Alpha
697       processor.
698
699       -mcpu
700           This option specifies the target processor.  If an attempt is made
701           to assemble an instruction which will not execute on the target
702           processor, the assembler may either expand the instruction as a
703           macro or issue an error message.  This option is equivalent to the
704           ".arch" directive.
705
706           The following processor names are recognized: 21064, "21064a",
707           21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
708           "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
709           "ev67", "ev68".  The special name "all" may be used to allow the
710           assembler to accept instructions valid for any Alpha processor.
711
712           In order to support existing practice in OSF/1 with respect to
713           ".arch", and existing practice within MILO (the Linux ARC
714           bootloader), the numbered processor names (e.g. 21064) enable the
715           processor-specific PALcode instructions, while the "electro-vlasic"
716           names (e.g. "ev4") do not.
717
718       -mdebug
719       -no-mdebug
720           Enables or disables the generation of ".mdebug" encapsulation for
721           stabs directives and procedure descriptors.  The default is to
722           automatically enable ".mdebug" when the first stabs directive is
723           seen.
724
725       -relax
726           This option forces all relocations to be put into the object file,
727           instead of saving space and resolving some relocations at assembly
728           time.  Note that this option does not propagate all symbol
729           arithmetic into the object file, because not all symbol arithmetic
730           can be represented.  However, the option can still be useful in
731           specific applications.
732
733       -replace
734       -noreplace
735           Enables or disables the optimization of procedure calls, both at
736           assemblage and at link time.  These options are only available for
737           VMS targets and "-replace" is the default.  See section 1.4.1 of
738           the OpenVMS Linker Utility Manual.
739
740       -g  This option is used when the compiler generates debug information.
741           When gcc is using mips-tfile to generate debug information for
742           ECOFF, local labels must be passed through to the object file.
743           Otherwise this option has no effect.
744
745       -Gsize
746           A local common symbol larger than size is placed in ".bss", while
747           smaller symbols are placed in ".sbss".
748
749       -F
750       -32addr
751           These options are ignored for backward compatibility.
752
753       The following options are available when as is configured for an ARC
754       processor.
755
756       -mcpu=cpu
757           This option selects the core processor variant.
758
759       -EB | -EL
760           Select either big-endian (-EB) or little-endian (-EL) output.
761
762       -mcode-density
763           Enable Code Density extenssion instructions.
764
765       The following options are available when as is configured for the ARM
766       processor family.
767
768       -mcpu=processor[+extension...]
769           Specify which ARM processor variant is the target.
770
771       -march=architecture[+extension...]
772           Specify which ARM architecture variant is used by the target.
773
774       -mfpu=floating-point-format
775           Select which Floating Point architecture is the target.
776
777       -mfloat-abi=abi
778           Select which floating point ABI is in use.
779
780       -mthumb
781           Enable Thumb only instruction decoding.
782
783       -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
784           Select which procedure calling convention is in use.
785
786       -EB | -EL
787           Select either big-endian (-EB) or little-endian (-EL) output.
788
789       -mthumb-interwork
790           Specify that the code has been generated with interworking between
791           Thumb and ARM code in mind.
792
793       -mccs
794           Turns on CodeComposer Studio assembly syntax compatibility mode.
795
796       -k  Specify that PIC code has been generated.
797
798       The following options are available when as is configured for the
799       Blackfin processor family.
800
801       -mcpu=processor[-sirevision]
802           This option specifies the target processor.  The optional
803           sirevision is not used in assembler.  It's here such that GCC can
804           easily pass down its "-mcpu=" option.  The assembler will issue an
805           error message if an attempt is made to assemble an instruction
806           which will not execute on the target processor.  The following
807           processor names are recognized: "bf504", "bf506", "bf512", "bf514",
808           "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
809           "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
810           implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
811           "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
812           "bf549", "bf549m", "bf561", and "bf592".
813
814       -mfdpic
815           Assemble for the FDPIC ABI.
816
817       -mno-fdpic
818       -mnopic
819           Disable -mfdpic.
820
821       The following options are available when as is configured for the Linux
822       kernel BPF processor family.
823
824       @chapter BPF Dependent Features
825
826   Options
827       -EB This option specifies that the assembler should emit big-endian
828           eBPF.
829
830       -EL This option specifies that the assembler should emit little-endian
831           eBPF.
832
833       Note that if no endianness option is specified in the command line, the
834       host endianness is used.  See the info pages for documentation of the
835       CRIS-specific options.
836
837       The following options are available when as is configured for the C-SKY
838       processor family.
839
840       -march=archname
841           Assemble for architecture archname.  The --help option lists valid
842           values for archname.
843
844       -mcpu=cpuname
845           Assemble for architecture cpuname.  The --help option lists valid
846           values for cpuname.
847
848       -EL
849       -mlittle-endian
850           Generate little-endian output.
851
852       -EB
853       -mbig-endian
854           Generate big-endian output.
855
856       -fpic
857       -pic
858           Generate position-independent code.
859
860       -mljump
861       -mno-ljump
862           Enable/disable transformation of the short branch instructions
863           "jbf", "jbt", and "jbr" to "jmpi".  This option is for V2
864           processors only.  It is ignored on CK801 and CK802 targets, which
865           do not support the "jmpi" instruction, and is enabled by default
866           for other processors.
867
868       -mbranch-stub
869       -mno-branch-stub
870           Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
871           instructions to the linker.
872
873           This option is only available for bare-metal C-SKY V2 ELF targets,
874           where it is enabled by default.  It cannot be used in code that
875           will be dynamically linked against shared libraries.
876
877       -force2bsr
878       -mforce2bsr
879       -no-force2bsr
880       -mno-force2bsr
881           Enable/disable transformation of "jbsr" instructions to "bsr".
882           This option is always enabled (and -mno-force2bsr is ignored) for
883           CK801/CK802 targets.  It is also always enabled when -mbranch-stub
884           is in effect.
885
886       -jsri2bsr
887       -mjsri2bsr
888       -no-jsri2bsr
889       -mno-jsri2bsr
890           Enable/disable transformation of "jsri" instructions to "bsr".
891           This option is enabled by default.
892
893       -mnolrw
894       -mno-lrw
895           Enable/disable transformation of "lrw" instructions into a
896           "movih"/"ori" pair.
897
898       -melrw
899       -mno-elrw
900           Enable/disable extended "lrw" instructions.  This option is enabled
901           by default for CK800-series processors.
902
903       -mlaf
904       -mliterals-after-func
905       -mno-laf
906       -mno-literals-after-func
907           Enable/disable placement of literal pools after each function.
908
909       -mlabr
910       -mliterals-after-br
911       -mno-labr
912       -mnoliterals-after-br
913           Enable/disable placement of literal pools after unconditional
914           branches.  This option is enabled by default.
915
916       -mistack
917       -mno-istack
918           Enable/disable interrupt stack instructions.  This option is
919           enabled by default on CK801, CK802, and CK802 processors.
920
921       The following options explicitly enable certain optional instructions.
922       These features are also enabled implicitly by using "-mcpu=" to specify
923       a processor that supports it.
924
925       -mhard-float
926           Enable hard float instructions.
927
928       -mmp
929           Enable multiprocessor instructions.
930
931       -mcp
932           Enable coprocessor instructions.
933
934       -mcache
935           Enable cache prefetch instruction.
936
937       -msecurity
938           Enable C-SKY security instructions.
939
940       -mtrust
941           Enable C-SKY trust instructions.
942
943       -mdsp
944           Enable DSP instructions.
945
946       -medsp
947           Enable enhanced DSP instructions.
948
949       -mvdsp
950           Enable vector DSP instructions.
951
952       The following options are available when as is configured for an
953       Epiphany processor.
954
955       -mepiphany
956           Specifies that the both 32 and 16 bit instructions are allowed.
957           This is the default behavior.
958
959       -mepiphany16
960           Restricts the permitted instructions to just the 16 bit set.
961
962       The following options are available when as is configured for an H8/300
963       processor.  @chapter H8/300 Dependent Features
964
965   Options
966       The Renesas H8/300 version of "as" has one machine-dependent option:
967
968       -h-tick-hex
969           Support H'00 style hex constants in addition to 0x00 style.
970
971       -mach=name
972           Sets the H8300 machine variant.  The following machine names are
973           recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
974           "h8300sxn".
975
976       The following options are available when as is configured for an i386
977       processor.
978
979       --32 | --x32 | --64
980           Select the word size, either 32 bits or 64 bits.  --32 implies
981           Intel i386 architecture, while --x32 and --64 imply AMD x86-64
982           architecture with 32-bit or 64-bit word-size respectively.
983
984           These options are only available with the ELF object file format,
985           and require that the necessary BFD support has been included (on a
986           32-bit platform you have to add --enable-64-bit-bfd to configure
987           enable 64-bit usage and use x86-64 as target platform).
988
989       -n  By default, x86 GAS replaces multiple nop instructions used for
990           alignment within code sections with multi-byte nop instructions
991           such as leal 0(%esi,1),%esi.  This switch disables the optimization
992           if a single byte nop (0x90) is explicitly specified as the fill
993           byte for alignment.
994
995       --divide
996           On SVR4-derived platforms, the character / is treated as a comment
997           character, which means that it cannot be used in expressions.  The
998           --divide option turns / into a normal character.  This does not
999           disable / at the beginning of a line starting a comment, or affect
1000           using # for starting a comment.
1001
1002       -march=CPU[+EXTENSION...]
1003           This option specifies the target processor.  The assembler will
1004           issue an error message if an attempt is made to assemble an
1005           instruction which will not execute on the target processor.  The
1006           following processor names are recognized: "i8086", "i186", "i286",
1007           "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
1008           "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
1009           "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
1010           "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
1011           "bdver3", "bdver4", "znver1", "znver2", "btver1", "btver2",
1012           "generic32" and "generic64".
1013
1014           In addition to the basic instruction set, the assembler can be told
1015           to accept various extension mnemonics.  For example,
1016           "-march=i686+sse4+vmx" extends i686 with sse4 and vmx.  The
1017           following extensions are currently supported: 8087, 287, 387, 687,
1018           "no87", "no287", "no387", "no687", "cmov", "nocmov", "fxsr",
1019           "nofxsr", "mmx", "nommx", "sse", "sse2", "sse3", "sse4a", "ssse3",
1020           "sse4.1", "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nosse4a",
1021           "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2",
1022           "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap", "mpx", "sha",
1023           "rdpid", "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq",
1024           "prefetchwt1", "clflushopt", "se1", "clwb", "movdiri", "movdir64b",
1025           "enqcmd", "serialize", "tsxldtrk", "avx512f", "avx512cd",
1026           "avx512er", "avx512pf", "avx512vl", "avx512bw", "avx512dq",
1027           "avx512ifma", "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw",
1028           "avx512_vpopcntdq", "avx512_vbmi2", "avx512_vnni", "avx512_bitalg",
1029           "avx512_vp2intersect", "avx512_bf16", "noavx512f", "noavx512cd",
1030           "noavx512er", "noavx512pf", "noavx512vl", "noavx512bw",
1031           "noavx512dq", "noavx512ifma", "noavx512vbmi", "noavx512_4fmaps",
1032           "noavx512_4vnniw", "noavx512_vpopcntdq", "noavx512_vbmi2",
1033           "noavx512_vnni", "noavx512_bitalg", "noavx512_vp2intersect",
1034           "noavx512_bf16", "noenqcmd", "noserialize", "notsxldtrk", "vmx",
1035           "vmfunc", "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes",
1036           "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe",
1037           "ept", "lzcnt", "popcnt", "hle", "rtm", "invpcid", "clflush",
1038           "mwaitx", "clzero", "wbnoinvd", "pconfig", "waitpkg", "cldemote",
1039           "rdpru", "mcommit", "sev_es", "lwp", "fma4", "xop", "cx16",
1040           "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "svme" and
1041           "padlock".  Note that rather than extending a basic instruction
1042           set, the extension mnemonics starting with "no" revoke the
1043           respective functionality.
1044
1045           When the ".arch" directive is used with -march, the ".arch"
1046           directive will take precedent.
1047
1048       -mtune=CPU
1049           This option specifies a processor to optimize for. When used in
1050           conjunction with the -march option, only instructions of the
1051           processor specified by the -march option will be generated.
1052
1053           Valid CPU values are identical to the processor list of -march=CPU.
1054
1055       -msse2avx
1056           This option specifies that the assembler should encode SSE
1057           instructions with VEX prefix.
1058
1059       -msse-check=none
1060       -msse-check=warning
1061       -msse-check=error
1062           These options control if the assembler should check SSE
1063           instructions.  -msse-check=none will make the assembler not to
1064           check SSE instructions,  which is the default.  -msse-check=warning
1065           will make the assembler issue a warning for any SSE instruction.
1066           -msse-check=error will make the assembler issue an error for any
1067           SSE instruction.
1068
1069       -mavxscalar=128
1070       -mavxscalar=256
1071           These options control how the assembler should encode scalar AVX
1072           instructions.  -mavxscalar=128 will encode scalar AVX instructions
1073           with 128bit vector length, which is the default.  -mavxscalar=256
1074           will encode scalar AVX instructions with 256bit vector length.
1075
1076           WARNING: Don't use this for production code - due to CPU errata the
1077           resulting code may not work on certain models.
1078
1079       -mvexwig=0
1080       -mvexwig=1
1081           These options control how the assembler should encode VEX.W-ignored
1082           (WIG) VEX instructions.  -mvexwig=0 will encode WIG VEX
1083           instructions with vex.w = 0, which is the default.  -mvexwig=1 will
1084           encode WIG EVEX instructions with vex.w = 1.
1085
1086           WARNING: Don't use this for production code - due to CPU errata the
1087           resulting code may not work on certain models.
1088
1089       -mevexlig=128
1090       -mevexlig=256
1091       -mevexlig=512
1092           These options control how the assembler should encode length-
1093           ignored (LIG) EVEX instructions.  -mevexlig=128 will encode LIG
1094           EVEX instructions with 128bit vector length, which is the default.
1095           -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1096           with 256bit and 512bit vector length, respectively.
1097
1098       -mevexwig=0
1099       -mevexwig=1
1100           These options control how the assembler should encode w-ignored
1101           (WIG) EVEX instructions.  -mevexwig=0 will encode WIG EVEX
1102           instructions with evex.w = 0, which is the default.  -mevexwig=1
1103           will encode WIG EVEX instructions with evex.w = 1.
1104
1105       -mmnemonic=att
1106       -mmnemonic=intel
1107           This option specifies instruction mnemonic for matching
1108           instructions.  The ".att_mnemonic" and ".intel_mnemonic" directives
1109           will take precedent.
1110
1111       -msyntax=att
1112       -msyntax=intel
1113           This option specifies instruction syntax when processing
1114           instructions.  The ".att_syntax" and ".intel_syntax" directives
1115           will take precedent.
1116
1117       -mnaked-reg
1118           This option specifies that registers don't require a % prefix.  The
1119           ".att_syntax" and ".intel_syntax" directives will take precedent.
1120
1121       -madd-bnd-prefix
1122           This option forces the assembler to add BND prefix to all branches,
1123           even if such prefix was not explicitly specified in the source
1124           code.
1125
1126       -mno-shared
1127           On ELF target, the assembler normally optimizes out non-PLT
1128           relocations against defined non-weak global branch targets with
1129           default visibility.  The -mshared option tells the assembler to
1130           generate code which may go into a shared library where all non-weak
1131           global branch targets with default visibility can be preempted.
1132           The resulting code is slightly bigger.  This option only affects
1133           the handling of branch instructions.
1134
1135       -mbig-obj
1136           On PE/COFF target this option forces the use of big object file
1137           format, which allows more than 32768 sections.
1138
1139       -momit-lock-prefix=no
1140       -momit-lock-prefix=yes
1141           These options control how the assembler should encode lock prefix.
1142           This option is intended as a workaround for processors, that fail
1143           on lock prefix. This option can only be safely used with single-
1144           core, single-thread computers -momit-lock-prefix=yes will omit all
1145           lock prefixes.  -momit-lock-prefix=no will encode lock prefix as
1146           usual, which is the default.
1147
1148       -mfence-as-lock-add=no
1149       -mfence-as-lock-add=yes
1150           These options control how the assembler should encode lfence,
1151           mfence and sfence.  -mfence-as-lock-add=yes will encode lfence,
1152           mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1153           addl $0x0, (%esp) in 32-bit mode.  -mfence-as-lock-add=no will
1154           encode lfence, mfence and sfence as usual, which is the default.
1155
1156       -mrelax-relocations=no
1157       -mrelax-relocations=yes
1158           These options control whether the assembler should generate relax
1159           relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1160           and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1161           -mrelax-relocations=yes will generate relax relocations.
1162           -mrelax-relocations=no will not generate relax relocations.  The
1163           default can be controlled by a configure option
1164           --enable-x86-relax-relocations.
1165
1166       -malign-branch-boundary=NUM
1167           This option controls how the assembler should align branches with
1168           segment prefixes or NOP.  NUM must be a power of 2.  It should be 0
1169           or no less than 16.  Branches will be aligned within NUM byte
1170           boundary.  -malign-branch-boundary=0, which is the default, doesn't
1171           align branches.
1172
1173       -malign-branch=TYPE[+TYPE...]
1174           This option specifies types of branches to align. TYPE is
1175           combination of jcc, which aligns conditional jumps, fused, which
1176           aligns fused conditional jumps, jmp, which aligns unconditional
1177           jumps, call which aligns calls, ret, which aligns rets, indirect,
1178           which aligns indirect jumps and calls.  The default is
1179           -malign-branch=jcc+fused+jmp.
1180
1181       -malign-branch-prefix-size=NUM
1182           This option specifies the maximum number of prefixes on an
1183           instruction to align branches.  NUM should be between 0 and 5.  The
1184           default NUM is 5.
1185
1186       -mbranches-within-32B-boundaries
1187           This option aligns conditional jumps, fused conditional jumps and
1188           unconditional jumps within 32 byte boundary with up to 5 segment
1189           prefixes on an instruction.  It is equivalent to
1190           -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp
1191           -malign-branch-prefix-size=5.  The default doesn't align branches.
1192
1193       -mlfence-after-load=no
1194       -mlfence-after-load=yes
1195           These options control whether the assembler should generate lfence
1196           after load instructions.  -mlfence-after-load=yes will generate
1197           lfence.  -mlfence-after-load=no will not generate lfence, which is
1198           the default.
1199
1200       -mlfence-before-indirect-branch=none
1201       -mlfence-before-indirect-branch=all
1202       -mlfence-before-indirect-branch=register
1203       -mlfence-before-indirect-branch=memory
1204           These options control whether the assembler should generate lfence
1205           before indirect near branch instructions.
1206           -mlfence-before-indirect-branch=all will generate lfence before
1207           indirect near branch via register and issue a warning before
1208           indirect near branch via memory.  It also implicitly sets
1209           -mlfence-before-ret=shl when there's no explict
1210           -mlfence-before-ret=.  -mlfence-before-indirect-branch=register
1211           will generate lfence before indirect near branch via register.
1212           -mlfence-before-indirect-branch=memory will issue a warning before
1213           indirect near branch via memory.
1214           -mlfence-before-indirect-branch=none will not generate lfence nor
1215           issue warning, which is the default.  Note that lfence won't be
1216           generated before indirect near branch via register with
1217           -mlfence-after-load=yes since lfence will be generated after
1218           loading branch target register.
1219
1220       -mlfence-before-ret=none
1221       -mlfence-before-ret=shl
1222       -mlfence-before-ret=or
1223       -mlfence-before-ret=yes
1224       -mlfence-before-ret=not
1225           These options control whether the assembler should generate lfence
1226           before ret.  -mlfence-before-ret=or will generate generate or
1227           instruction with lfence.  -mlfence-before-ret=shl/yes will generate
1228           shl instruction with lfence. -mlfence-before-ret=not will generate
1229           not instruction with lfence. -mlfence-before-ret=none will not
1230           generate lfence, which is the default.
1231
1232       -mx86-used-note=no
1233       -mx86-used-note=yes
1234           These options control whether the assembler should generate
1235           GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1236           property notes.  The default can be controlled by the
1237           --enable-x86-used-note configure option.
1238
1239       -mevexrcig=rne
1240       -mevexrcig=rd
1241       -mevexrcig=ru
1242       -mevexrcig=rz
1243           These options control how the assembler should encode SAE-only EVEX
1244           instructions.  -mevexrcig=rne will encode RC bits of EVEX
1245           instruction with 00, which is the default.  -mevexrcig=rd,
1246           -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1247           instructions with 01, 10 and 11 RC bits, respectively.
1248
1249       -mamd64
1250       -mintel64
1251           This option specifies that the assembler should accept only AMD64
1252           or Intel64 ISA in 64-bit mode.  The default is to accept common,
1253           Intel64 only and AMD64 ISAs.
1254
1255       -O0 | -O | -O1 | -O2 | -Os
1256           Optimize instruction encoding with smaller instruction size.  -O
1257           and -O1 encode 64-bit register load instructions with 64-bit
1258           immediate as 32-bit register load instructions with 31-bit or
1259           32-bits immediates, encode 64-bit register clearing instructions
1260           with 32-bit register clearing instructions, encode 256-bit/512-bit
1261           VEX/EVEX vector register clearing instructions with 128-bit VEX
1262           vector register clearing instructions, encode 128-bit/256-bit EVEX
1263           vector register load/store instructions with VEX vector register
1264           load/store instructions, and encode 128-bit/256-bit EVEX packed
1265           integer logical instructions with 128-bit/256-bit VEX packed
1266           integer logical.
1267
1268           -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX
1269           vector register clearing instructions with 128-bit EVEX vector
1270           register clearing instructions.  In 64-bit mode VEX encoded
1271           instructions with commutative source operands will also have their
1272           source operands swapped if this allows using the 2-byte VEX prefix
1273           form instead of the 3-byte one.  Certain forms of AND as well as OR
1274           with the same (register) operand specified twice will also be
1275           changed to TEST.
1276
1277           -Os includes -O2 optimization plus encodes 16-bit, 32-bit and
1278           64-bit register tests with immediate as 8-bit register test with
1279           immediate.  -O0 turns off this optimization.
1280
1281       The following options are available when as is configured for the
1282       Ubicom IP2K series.
1283
1284       -mip2022ext
1285           Specifies that the extended IP2022 instructions are allowed.
1286
1287       -mip2022
1288           Restores the default behaviour, which restricts the permitted
1289           instructions to just the basic IP2022 ones.
1290
1291       The following options are available when as is configured for the
1292       Renesas M32C and M16C processors.
1293
1294       -m32c
1295           Assemble M32C instructions.
1296
1297       -m16c
1298           Assemble M16C instructions (the default).
1299
1300       -relax
1301           Enable support for link-time relaxations.
1302
1303       -h-tick-hex
1304           Support H'00 style hex constants in addition to 0x00 style.
1305
1306       The following options are available when as is configured for the
1307       Renesas M32R (formerly Mitsubishi M32R) series.
1308
1309       --m32rx
1310           Specify which processor in the M32R family is the target.  The
1311           default is normally the M32R, but this option changes it to the
1312           M32RX.
1313
1314       --warn-explicit-parallel-conflicts or --Wp
1315           Produce warning messages when questionable parallel constructs are
1316           encountered.
1317
1318       --no-warn-explicit-parallel-conflicts or --Wnp
1319           Do not produce warning messages when questionable parallel
1320           constructs are encountered.
1321
1322       The following options are available when as is configured for the
1323       Motorola 68000 series.
1324
1325       -l  Shorten references to undefined symbols, to one word instead of
1326           two.
1327
1328       -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1329       | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1330       | -m68333 | -m68340 | -mcpu32 | -m5200
1331           Specify what processor in the 68000 family is the target.  The
1332           default is normally the 68020, but this can be changed at
1333           configuration time.
1334
1335       -m68881 | -m68882 | -mno-68881 | -mno-68882
1336           The target machine does (or does not) have a floating-point
1337           coprocessor.  The default is to assume a coprocessor for 68020,
1338           68030, and cpu32.  Although the basic 68000 is not compatible with
1339           the 68881, a combination of the two can be specified, since it's
1340           possible to do emulation of the coprocessor instructions with the
1341           main processor.
1342
1343       -m68851 | -mno-68851
1344           The target machine does (or does not) have a memory-management unit
1345           coprocessor.  The default is to assume an MMU for 68020 and up.
1346
1347       The following options are available when as is configured for an Altera
1348       Nios II processor.
1349
1350       -relax-section
1351           Replace identified out-of-range branches with PC-relative "jmp"
1352           sequences when possible.  The generated code sequences are suitable
1353           for use in position-independent code, but there is a practical
1354           limit on the extended branch range because of the length of the
1355           sequences.  This option is the default.
1356
1357       -relax-all
1358           Replace branch instructions not determinable to be in range and all
1359           call instructions with "jmp" and "callr" sequences (respectively).
1360           This option generates absolute relocations against the target
1361           symbols and is not appropriate for position-independent code.
1362
1363       -no-relax
1364           Do not replace any branches or calls.
1365
1366       -EB Generate big-endian output.
1367
1368       -EL Generate little-endian output.  This is the default.
1369
1370       -march=architecture
1371           This option specifies the target architecture.  The assembler
1372           issues an error message if an attempt is made to assemble an
1373           instruction which will not execute on the target architecture.  The
1374           following architecture names are recognized: "r1", "r2".  The
1375           default is "r1".
1376
1377       The following options are available when as is configured for a PRU
1378       processor.
1379
1380       -mlink-relax
1381           Assume that LD would optimize LDI32 instructions by checking the
1382           upper 16 bits of the expression. If they are all zeros, then LD
1383           would shorten the LDI32 instruction to a single LDI. In such case
1384           "as" will output DIFF relocations for diff expressions.
1385
1386       -mno-link-relax
1387           Assume that LD would not optimize LDI32 instructions. As a
1388           consequence, DIFF relocations will not be emitted.
1389
1390       -mno-warn-regname-label
1391           Do not warn if a label name matches a register name. Usually
1392           assembler programmers will want this warning to be emitted. C
1393           compilers may want to turn this off.
1394
1395       The following options are available when as is configured for a MIPS
1396       processor.
1397
1398       -G num
1399           This option sets the largest size of an object that can be
1400           referenced implicitly with the "gp" register.  It is only accepted
1401           for targets that use ECOFF format, such as a DECstation running
1402           Ultrix.  The default value is 8.
1403
1404       -EB Generate "big endian" format output.
1405
1406       -EL Generate "little endian" format output.
1407
1408       -mips1
1409       -mips2
1410       -mips3
1411       -mips4
1412       -mips5
1413       -mips32
1414       -mips32r2
1415       -mips32r3
1416       -mips32r5
1417       -mips32r6
1418       -mips64
1419       -mips64r2
1420       -mips64r3
1421       -mips64r5
1422       -mips64r6
1423           Generate code for a particular MIPS Instruction Set Architecture
1424           level.  -mips1 is an alias for -march=r3000, -mips2 is an alias for
1425           -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1426           alias for -march=r8000.  -mips5, -mips32, -mips32r2, -mips32r3,
1427           -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1428           -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1429           MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1430           MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1431           Release 6 ISA processors, respectively.
1432
1433       -march=cpu
1434           Generate code for a particular MIPS CPU.
1435
1436       -mtune=cpu
1437           Schedule and tune for a particular MIPS CPU.
1438
1439       -mfix7000
1440       -mno-fix7000
1441           Cause nops to be inserted if the read of the destination register
1442           of an mfhi or mflo instruction occurs in the following two
1443           instructions.
1444
1445       -mfix-rm7000
1446       -mno-fix-rm7000
1447           Cause nops to be inserted if a dmult or dmultu instruction is
1448           followed by a load instruction.
1449
1450       -mfix-r5900
1451       -mno-fix-r5900
1452           Do not attempt to schedule the preceding instruction into the delay
1453           slot of a branch instruction placed at the end of a short loop of
1454           six instructions or fewer and always schedule a "nop" instruction
1455           there instead.  The short loop bug under certain conditions causes
1456           loops to execute only once or twice, due to a hardware bug in the
1457           R5900 chip.
1458
1459       -mdebug
1460       -no-mdebug
1461           Cause stabs-style debugging output to go into an ECOFF-style
1462           .mdebug section instead of the standard ELF .stabs sections.
1463
1464       -mpdr
1465       -mno-pdr
1466           Control generation of ".pdr" sections.
1467
1468       -mgp32
1469       -mfp32
1470           The register sizes are normally inferred from the ISA and ABI, but
1471           these flags force a certain group of registers to be treated as 32
1472           bits wide at all times.  -mgp32 controls the size of general-
1473           purpose registers and -mfp32 controls the size of floating-point
1474           registers.
1475
1476       -mgp64
1477       -mfp64
1478           The register sizes are normally inferred from the ISA and ABI, but
1479           these flags force a certain group of registers to be treated as 64
1480           bits wide at all times.  -mgp64 controls the size of general-
1481           purpose registers and -mfp64 controls the size of floating-point
1482           registers.
1483
1484       -mfpxx
1485           The register sizes are normally inferred from the ISA and ABI, but
1486           using this flag in combination with -mabi=32 enables an ABI variant
1487           which will operate correctly with floating-point registers which
1488           are 32 or 64 bits wide.
1489
1490       -modd-spreg
1491       -mno-odd-spreg
1492           Enable use of floating-point operations on odd-numbered single-
1493           precision registers when supported by the ISA.  -mfpxx implies
1494           -mno-odd-spreg, otherwise the default is -modd-spreg.
1495
1496       -mips16
1497       -no-mips16
1498           Generate code for the MIPS 16 processor.  This is equivalent to
1499           putting ".module mips16" at the start of the assembly file.
1500           -no-mips16 turns off this option.
1501
1502       -mmips16e2
1503       -mno-mips16e2
1504           Enable the use of MIPS16e2 instructions in MIPS16 mode.  This is
1505           equivalent to putting ".module mips16e2" at the start of the
1506           assembly file.  -mno-mips16e2 turns off this option.
1507
1508       -mmicromips
1509       -mno-micromips
1510           Generate code for the microMIPS processor.  This is equivalent to
1511           putting ".module micromips" at the start of the assembly file.
1512           -mno-micromips turns off this option.  This is equivalent to
1513           putting ".module nomicromips" at the start of the assembly file.
1514
1515       -msmartmips
1516       -mno-smartmips
1517           Enables the SmartMIPS extension to the MIPS32 instruction set.
1518           This is equivalent to putting ".module smartmips" at the start of
1519           the assembly file.  -mno-smartmips turns off this option.
1520
1521       -mips3d
1522       -no-mips3d
1523           Generate code for the MIPS-3D Application Specific Extension.  This
1524           tells the assembler to accept MIPS-3D instructions.  -no-mips3d
1525           turns off this option.
1526
1527       -mdmx
1528       -no-mdmx
1529           Generate code for the MDMX Application Specific Extension.  This
1530           tells the assembler to accept MDMX instructions.  -no-mdmx turns
1531           off this option.
1532
1533       -mdsp
1534       -mno-dsp
1535           Generate code for the DSP Release 1 Application Specific Extension.
1536           This tells the assembler to accept DSP Release 1 instructions.
1537           -mno-dsp turns off this option.
1538
1539       -mdspr2
1540       -mno-dspr2
1541           Generate code for the DSP Release 2 Application Specific Extension.
1542           This option implies -mdsp.  This tells the assembler to accept DSP
1543           Release 2 instructions.  -mno-dspr2 turns off this option.
1544
1545       -mdspr3
1546       -mno-dspr3
1547           Generate code for the DSP Release 3 Application Specific Extension.
1548           This option implies -mdsp and -mdspr2.  This tells the assembler to
1549           accept DSP Release 3 instructions.  -mno-dspr3 turns off this
1550           option.
1551
1552       -mmsa
1553       -mno-msa
1554           Generate code for the MIPS SIMD Architecture Extension.  This tells
1555           the assembler to accept MSA instructions.  -mno-msa turns off this
1556           option.
1557
1558       -mxpa
1559       -mno-xpa
1560           Generate code for the MIPS eXtended Physical Address (XPA)
1561           Extension.  This tells the assembler to accept XPA instructions.
1562           -mno-xpa turns off this option.
1563
1564       -mmt
1565       -mno-mt
1566           Generate code for the MT Application Specific Extension.  This
1567           tells the assembler to accept MT instructions.  -mno-mt turns off
1568           this option.
1569
1570       -mmcu
1571       -mno-mcu
1572           Generate code for the MCU Application Specific Extension.  This
1573           tells the assembler to accept MCU instructions.  -mno-mcu turns off
1574           this option.
1575
1576       -mcrc
1577       -mno-crc
1578           Generate code for the MIPS cyclic redundancy check (CRC)
1579           Application Specific Extension.  This tells the assembler to accept
1580           CRC instructions.  -mno-crc turns off this option.
1581
1582       -mginv
1583       -mno-ginv
1584           Generate code for the Global INValidate (GINV) Application Specific
1585           Extension.  This tells the assembler to accept GINV instructions.
1586           -mno-ginv turns off this option.
1587
1588       -mloongson-mmi
1589       -mno-loongson-mmi
1590           Generate code for the Loongson MultiMedia extensions Instructions
1591           (MMI) Application Specific Extension.  This tells the assembler to
1592           accept MMI instructions.  -mno-loongson-mmi turns off this option.
1593
1594       -mloongson-cam
1595       -mno-loongson-cam
1596           Generate code for the Loongson Content Address Memory (CAM)
1597           instructions.  This tells the assembler to accept Loongson CAM
1598           instructions.  -mno-loongson-cam turns off this option.
1599
1600       -mloongson-ext
1601       -mno-loongson-ext
1602           Generate code for the Loongson EXTensions (EXT) instructions.  This
1603           tells the assembler to accept Loongson EXT instructions.
1604           -mno-loongson-ext turns off this option.
1605
1606       -mloongson-ext2
1607       -mno-loongson-ext2
1608           Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1609           This option implies -mloongson-ext.  This tells the assembler to
1610           accept Loongson EXT2 instructions.  -mno-loongson-ext2 turns off
1611           this option.
1612
1613       -minsn32
1614       -mno-insn32
1615           Only use 32-bit instruction encodings when generating code for the
1616           microMIPS processor.  This option inhibits the use of any 16-bit
1617           instructions.  This is equivalent to putting ".set insn32" at the
1618           start of the assembly file.  -mno-insn32 turns off this option.
1619           This is equivalent to putting ".set noinsn32" at the start of the
1620           assembly file.  By default -mno-insn32 is selected, allowing all
1621           instructions to be used.
1622
1623       --construct-floats
1624       --no-construct-floats
1625           The --no-construct-floats option disables the construction of
1626           double width floating point constants by loading the two halves of
1627           the value into the two single width floating point registers that
1628           make up the double width register.  By default --construct-floats
1629           is selected, allowing construction of these floating point
1630           constants.
1631
1632       --relax-branch
1633       --no-relax-branch
1634           The --relax-branch option enables the relaxation of out-of-range
1635           branches.  By default --no-relax-branch is selected, causing any
1636           out-of-range branches to produce an error.
1637
1638       -mignore-branch-isa
1639       -mno-ignore-branch-isa
1640           Ignore branch checks for invalid transitions between ISA modes.
1641           The semantics of branches does not provide for an ISA mode switch,
1642           so in most cases the ISA mode a branch has been encoded for has to
1643           be the same as the ISA mode of the branch's target label.
1644           Therefore GAS has checks implemented that verify in branch assembly
1645           that the two ISA modes match.  -mignore-branch-isa disables these
1646           checks.  By default -mno-ignore-branch-isa is selected, causing any
1647           invalid branch requiring a transition between ISA modes to produce
1648           an error.
1649
1650       -mnan=encoding
1651           Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1652           (-mnan=legacy) NaN encoding format.  The latter is the default.
1653
1654       --emulation=name
1655           This option was formerly used to switch between ELF and ECOFF
1656           output on targets like IRIX 5 that supported both.  MIPS ECOFF
1657           support was removed in GAS 2.24, so the option now serves little
1658           purpose.  It is retained for backwards compatibility.
1659
1660           The available configuration names are: mipself, mipslelf and
1661           mipsbelf.  Choosing mipself now has no effect, since the output is
1662           always ELF.  mipslelf and mipsbelf select little- and big-endian
1663           output respectively, but -EL and -EB are now the preferred options
1664           instead.
1665
1666       -nocpp
1667           as ignores this option.  It is accepted for compatibility with the
1668           native tools.
1669
1670       --trap
1671       --no-trap
1672       --break
1673       --no-break
1674           Control how to deal with multiplication overflow and division by
1675           zero.  --trap or --no-break (which are synonyms) take a trap
1676           exception (and only work for Instruction Set Architecture level 2
1677           and higher); --break or --no-trap (also synonyms, and the default)
1678           take a break exception.
1679
1680       -n  When this option is used, as will issue a warning every time it
1681           generates a nop instruction from a macro.
1682
1683       The following options are available when as is configured for a Meta
1684       processor.
1685
1686       "-mcpu=metac11"
1687           Generate code for Meta 1.1.
1688
1689       "-mcpu=metac12"
1690           Generate code for Meta 1.2.
1691
1692       "-mcpu=metac21"
1693           Generate code for Meta 2.1.
1694
1695       "-mfpu=metac21"
1696           Allow code to use FPU hardware of Meta 2.1.
1697
1698       See the info pages for documentation of the MMIX-specific options.
1699
1700       The following options are available when as is configured for a NDS32
1701       processor.
1702
1703       "-O1"
1704           Optimize for performance.
1705
1706       "-Os"
1707           Optimize for space.
1708
1709       "-EL"
1710           Produce little endian data output.
1711
1712       "-EB"
1713           Produce little endian data output.
1714
1715       "-mpic"
1716           Generate PIC.
1717
1718       "-mno-fp-as-gp-relax"
1719           Suppress fp-as-gp relaxation for this file.
1720
1721       "-mb2bb-relax"
1722           Back-to-back branch optimization.
1723
1724       "-mno-all-relax"
1725           Suppress all relaxation for this file.
1726
1727       "-march=<arch name>"
1728           Assemble for architecture <arch name> which could be v3, v3j, v3m,
1729           v3f, v3s, v2, v2j, v2f, v2s.
1730
1731       "-mbaseline=<baseline>"
1732           Assemble for baseline <baseline> which could be v2, v3, v3m.
1733
1734       "-mfpu-freg=FREG"
1735           Specify a FPU configuration.
1736
1737           "0      8 SP /  4 DP registers"
1738           "1     16 SP /  8 DP registers"
1739           "2     32 SP / 16 DP registers"
1740           "3     32 SP / 32 DP registers"
1741       "-mabi=abi"
1742           Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1743
1744       "-m[no-]mac"
1745           Enable/Disable Multiply instructions support.
1746
1747       "-m[no-]div"
1748           Enable/Disable Divide instructions support.
1749
1750       "-m[no-]16bit-ext"
1751           Enable/Disable 16-bit extension
1752
1753       "-m[no-]dx-regs"
1754           Enable/Disable d0/d1 registers
1755
1756       "-m[no-]perf-ext"
1757           Enable/Disable Performance extension
1758
1759       "-m[no-]perf2-ext"
1760           Enable/Disable Performance extension 2
1761
1762       "-m[no-]string-ext"
1763           Enable/Disable String extension
1764
1765       "-m[no-]reduced-regs"
1766           Enable/Disable Reduced Register configuration (GPR16) option
1767
1768       "-m[no-]audio-isa-ext"
1769           Enable/Disable AUDIO ISA extension
1770
1771       "-m[no-]fpu-sp-ext"
1772           Enable/Disable FPU SP extension
1773
1774       "-m[no-]fpu-dp-ext"
1775           Enable/Disable FPU DP extension
1776
1777       "-m[no-]fpu-fma"
1778           Enable/Disable FPU fused-multiply-add instructions
1779
1780       "-mall-ext"
1781           Turn on all extensions and instructions support
1782
1783       The following options are available when as is configured for a PowerPC
1784       processor.
1785
1786       -a32
1787           Generate ELF32 or XCOFF32.
1788
1789       -a64
1790           Generate ELF64 or XCOFF64.
1791
1792       -K PIC
1793           Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1794
1795       -mpwrx | -mpwr2
1796           Generate code for POWER/2 (RIOS2).
1797
1798       -mpwr
1799           Generate code for POWER (RIOS1)
1800
1801       -m601
1802           Generate code for PowerPC 601.
1803
1804       -mppc, -mppc32, -m603, -m604
1805           Generate code for PowerPC 603/604.
1806
1807       -m403, -m405
1808           Generate code for PowerPC 403/405.
1809
1810       -m440
1811           Generate code for PowerPC 440.  BookE and some 405 instructions.
1812
1813       -m464
1814           Generate code for PowerPC 464.
1815
1816       -m476
1817           Generate code for PowerPC 476.
1818
1819       -m7400, -m7410, -m7450, -m7455
1820           Generate code for PowerPC 7400/7410/7450/7455.
1821
1822       -m750cl, -mgekko, -mbroadway
1823           Generate code for PowerPC 750CL/Gekko/Broadway.
1824
1825       -m821, -m850, -m860
1826           Generate code for PowerPC 821/850/860.
1827
1828       -mppc64, -m620
1829           Generate code for PowerPC 620/625/630.
1830
1831       -me500, -me500x2
1832           Generate code for Motorola e500 core complex.
1833
1834       -me500mc
1835           Generate code for Freescale e500mc core complex.
1836
1837       -me500mc64
1838           Generate code for Freescale e500mc64 core complex.
1839
1840       -me5500
1841           Generate code for Freescale e5500 core complex.
1842
1843       -me6500
1844           Generate code for Freescale e6500 core complex.
1845
1846       -mspe
1847           Generate code for Motorola SPE instructions.
1848
1849       -mspe2
1850           Generate code for Freescale SPE2 instructions.
1851
1852       -mtitan
1853           Generate code for AppliedMicro Titan core complex.
1854
1855       -mppc64bridge
1856           Generate code for PowerPC 64, including bridge insns.
1857
1858       -mbooke
1859           Generate code for 32-bit BookE.
1860
1861       -ma2
1862           Generate code for A2 architecture.
1863
1864       -me300
1865           Generate code for PowerPC e300 family.
1866
1867       -maltivec
1868           Generate code for processors with AltiVec instructions.
1869
1870       -mvle
1871           Generate code for Freescale PowerPC VLE instructions.
1872
1873       -mvsx
1874           Generate code for processors with Vector-Scalar (VSX) instructions.
1875
1876       -mhtm
1877           Generate code for processors with Hardware Transactional Memory
1878           instructions.
1879
1880       -mpower4, -mpwr4
1881           Generate code for Power4 architecture.
1882
1883       -mpower5, -mpwr5, -mpwr5x
1884           Generate code for Power5 architecture.
1885
1886       -mpower6, -mpwr6
1887           Generate code for Power6 architecture.
1888
1889       -mpower7, -mpwr7
1890           Generate code for Power7 architecture.
1891
1892       -mpower8, -mpwr8
1893           Generate code for Power8 architecture.
1894
1895       -mpower9, -mpwr9
1896           Generate code for Power9 architecture.
1897
1898       -mpower10, -mpwr10
1899           Generate code for Power10 architecture.
1900
1901       -mcell
1902       -mcell
1903           Generate code for Cell Broadband Engine architecture.
1904
1905       -mcom
1906           Generate code Power/PowerPC common instructions.
1907
1908       -many
1909           Generate code for any architecture (PWR/PWRX/PPC).
1910
1911       -mregnames
1912           Allow symbolic names for registers.
1913
1914       -mno-regnames
1915           Do not allow symbolic names for registers.
1916
1917       -mrelocatable
1918           Support for GCC's -mrelocatable option.
1919
1920       -mrelocatable-lib
1921           Support for GCC's -mrelocatable-lib option.
1922
1923       -memb
1924           Set PPC_EMB bit in ELF flags.
1925
1926       -mlittle, -mlittle-endian, -le
1927           Generate code for a little endian machine.
1928
1929       -mbig, -mbig-endian, -be
1930           Generate code for a big endian machine.
1931
1932       -msolaris
1933           Generate code for Solaris.
1934
1935       -mno-solaris
1936           Do not generate code for Solaris.
1937
1938       -nops=count
1939           If an alignment directive inserts more than count nops, put a
1940           branch at the beginning to skip execution of the nops.
1941
1942       The following options are available when as is configured for a RISC-V
1943       processor.
1944
1945       -fpic
1946       -fPIC
1947           Generate position-independent code
1948
1949       -fno-pic
1950           Don't generate position-independent code (default)
1951
1952       -march=ISA
1953           Select the base isa, as specified by ISA.  For example
1954           -march=rv32ima.  If this option and the architecture attributes
1955           aren't set, then assembler will check the default configure setting
1956           --with-arch=ISA.
1957
1958       -misa-spec=ISAspec
1959           Select the default isa spec version.  If the version of ISA isn't
1960           set by -march, then assembler helps to set the version according to
1961           the default chosen spec.  If this option isn't set, then assembler
1962           will check the default configure setting --with-isa-spec=ISAspec.
1963
1964       -mpriv-spec=PRIVspec
1965           Select the privileged spec version.  We can decide whether the CSR
1966           is valid or not according to the chosen spec.  If this option and
1967           the privilege attributes aren't set, then assembler will check the
1968           default configure setting --with-priv-spec=PRIVspec.
1969
1970       -mabi=ABI
1971           Selects the ABI, which is either "ilp32" or "lp64", optionally
1972           followed by "f", "d", or "q" to indicate single-precision, double-
1973           precision, or quad-precision floating-point calling convention, or
1974           none to indicate the soft-float calling convention.  Also, "ilp32"
1975           can optionally be followed by "e" to indicate the RVE ABI, which is
1976           always soft-float.
1977
1978       -mrelax
1979           Take advantage of linker relaxations to reduce the number of
1980           instructions required to materialize symbol addresses. (default)
1981
1982       -mno-relax
1983           Don't do linker relaxations.
1984
1985       -march-attr
1986           Generate the default contents for the riscv elf attribute section
1987           if the .attribute directives are not set.  This section is used to
1988           record the information that a linker or runtime loader needs to
1989           check compatibility.  This information includes ISA string, stack
1990           alignment requirement, unaligned memory accesses, and the major,
1991           minor and revision version of privileged specification.
1992
1993       -mno-arch-attr
1994           Don't generate the default riscv elf attribute section if the
1995           .attribute directives are not set.
1996
1997       -mcsr-check
1998           Enable the CSR checking for the ISA-dependent CRS and the read-only
1999           CSR.  The ISA-dependent CSR are only valid when the specific ISA is
2000           set.  The read-only CSR can not be written by the CSR instructions.
2001
2002       -mno-csr-check
2003           Don't do CSR cheching.
2004
2005       See the info pages for documentation of the RX-specific options.
2006
2007       The following options are available when as is configured for the s390
2008       processor family.
2009
2010       -m31
2011       -m64
2012           Select the word size, either 31/32 bits or 64 bits.
2013
2014       -mesa
2015       -mzarch
2016           Select the architecture mode, either the Enterprise System
2017           Architecture (esa) or the z/Architecture mode (zarch).
2018
2019       -march=processor
2020           Specify which s390 processor variant is the target, g5 (or arch3),
2021           g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
2022           (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11),
2023           z14 (or arch12), or z15 (or arch13).
2024
2025       -mregnames
2026       -mno-regnames
2027           Allow or disallow symbolic names for registers.
2028
2029       -mwarn-areg-zero
2030           Warn whenever the operand for a base or index register has been
2031           specified but evaluates to zero.
2032
2033       The following options are available when as is configured for a
2034       TMS320C6000 processor.
2035
2036       -march=arch
2037           Enable (only) instructions from architecture arch.  By default, all
2038           instructions are permitted.
2039
2040           The following values of arch are accepted: "c62x", "c64x", "c64x+",
2041           "c67x", "c67x+", "c674x".
2042
2043       -mdsbt
2044       -mno-dsbt
2045           The -mdsbt option causes the assembler to generate the
2046           "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
2047           code is using DSBT addressing.  The -mno-dsbt option, the default,
2048           causes the tag to have a value of 0, indicating that the code does
2049           not use DSBT addressing.  The linker will emit a warning if objects
2050           of different type (DSBT and non-DSBT) are linked together.
2051
2052       -mpid=no
2053       -mpid=near
2054       -mpid=far
2055           The -mpid= option causes the assembler to generate the
2056           "Tag_ABI_PID" attribute with a value indicating the form of data
2057           addressing used by the code.  -mpid=no, the default, indicates
2058           position-dependent data addressing, -mpid=near indicates position-
2059           independent addressing with GOT accesses using near DP addressing,
2060           and -mpid=far indicates position-independent addressing with GOT
2061           accesses using far DP addressing.  The linker will emit a warning
2062           if objects built with different settings of this option are linked
2063           together.
2064
2065       -mpic
2066       -mno-pic
2067           The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
2068           attribute with a value of 1, indicating that the code is using
2069           position-independent code addressing,  The "-mno-pic" option, the
2070           default, causes the tag to have a value of 0, indicating position-
2071           dependent code addressing.  The linker will emit a warning if
2072           objects of different type (position-dependent and position-
2073           independent) are linked together.
2074
2075       -mbig-endian
2076       -mlittle-endian
2077           Generate code for the specified endianness.  The default is little-
2078           endian.
2079
2080       The following options are available when as is configured for a TILE-Gx
2081       processor.
2082
2083       -m32 | -m64
2084           Select the word size, either 32 bits or 64 bits.
2085
2086       -EB | -EL
2087           Select the endianness, either big-endian (-EB) or little-endian
2088           (-EL).
2089
2090       The following option is available when as is configured for a Visium
2091       processor.
2092
2093       -mtune=arch
2094           This option specifies the target architecture.  If an attempt is
2095           made to assemble an instruction that will not execute on the target
2096           architecture, the assembler will issue an error message.
2097
2098           The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
2099
2100       The following options are available when as is configured for an Xtensa
2101       processor.
2102
2103       --text-section-literals | --no-text-section-literals
2104           Control the treatment of literal pools.  The default is
2105           --no-text-section-literals, which places literals in separate
2106           sections in the output file.  This allows the literal pool to be
2107           placed in a data RAM/ROM.  With --text-section-literals, the
2108           literals are interspersed in the text section in order to keep them
2109           as close as possible to their references.  This may be necessary
2110           for large assembly files, where the literals would otherwise be out
2111           of range of the "L32R" instructions in the text section.  Literals
2112           are grouped into pools following ".literal_position" directives or
2113           preceding "ENTRY" instructions.  These options only affect literals
2114           referenced via PC-relative "L32R" instructions; literals for
2115           absolute mode "L32R" instructions are handled separately.
2116
2117       --auto-litpools | --no-auto-litpools
2118           Control the treatment of literal pools.  The default is
2119           --no-auto-litpools, which in the absence of --text-section-literals
2120           places literals in separate sections in the output file.  This
2121           allows the literal pool to be placed in a data RAM/ROM.  With
2122           --auto-litpools, the literals are interspersed in the text section
2123           in order to keep them as close as possible to their references,
2124           explicit ".literal_position" directives are not required.  This may
2125           be necessary for very large functions, where single literal pool at
2126           the beginning of the function may not be reachable by "L32R"
2127           instructions at the end.  These options only affect literals
2128           referenced via PC-relative "L32R" instructions; literals for
2129           absolute mode "L32R" instructions are handled separately.  When
2130           used together with --text-section-literals, --auto-litpools takes
2131           precedence.
2132
2133       --absolute-literals | --no-absolute-literals
2134           Indicate to the assembler whether "L32R" instructions use absolute
2135           or PC-relative addressing.  If the processor includes the absolute
2136           addressing option, the default is to use absolute "L32R"
2137           relocations.  Otherwise, only the PC-relative "L32R" relocations
2138           can be used.
2139
2140       --target-align | --no-target-align
2141           Enable or disable automatic alignment to reduce branch penalties at
2142           some expense in code size.    This optimization is enabled by
2143           default.  Note that the assembler will always align instructions
2144           like "LOOP" that have fixed alignment requirements.
2145
2146       --longcalls | --no-longcalls
2147           Enable or disable transformation of call instructions to allow
2148           calls across a greater range of addresses.    This option should be
2149           used when call targets can potentially be out of range.  It may
2150           degrade both code size and performance, but the linker can
2151           generally optimize away the unnecessary overhead when a call ends
2152           up within range.  The default is --no-longcalls.
2153
2154       --transform | --no-transform
2155           Enable or disable all assembler transformations of Xtensa
2156           instructions, including both relaxation and optimization.  The
2157           default is --transform; --no-transform should only be used in the
2158           rare cases when the instructions must be exactly as specified in
2159           the assembly source.  Using --no-transform causes out of range
2160           instruction operands to be errors.
2161
2162       --rename-section oldname=newname
2163           Rename the oldname section to newname.  This option can be used
2164           multiple times to rename multiple sections.
2165
2166       --trampolines | --no-trampolines
2167           Enable or disable transformation of jump instructions to allow
2168           jumps across a greater range of addresses.    This option should be
2169           used when jump targets can potentially be out of range.  In the
2170           absence of such jumps this option does not affect code size or
2171           performance.  The default is --trampolines.
2172
2173       --abi-windowed | --abi-call0
2174           Choose ABI tag written to the ".xtensa.info" section.  ABI tag
2175           indicates ABI of the assembly code.  A warning is issued by the
2176           linker on an attempt to link object files with inconsistent ABI
2177           tags.  Default ABI is chosen by the Xtensa core configuration.
2178
2179       The following options are available when as is configured for an Z80
2180       processor.
2181
2182       @chapter Z80 Dependent Features
2183
2184   Command-line Options
2185       -march=CPU[-EXT...][+EXT...]
2186           This option specifies the target processor. The assembler will
2187           issue an error message if an attempt is made to assemble an
2188           instruction which will not execute on the target processor. The
2189           following processor names are recognized: "z80", "z180", "ez80",
2190           "gbz80", "z80n", "r800".  In addition to the basic instruction set,
2191           the assembler can be told to accept some extention mnemonics. For
2192           example, "-march=z180+sli+infc" extends z180 with SLI instructions
2193           and IN F,(C). The following extentions are currently supported:
2194           "full" (all known instructions), "adl" (ADL CPU mode by default,
2195           eZ80 only), "sli" (instruction known as SLI, SLL or SL1), "xyhl"
2196           (instructions with halves of index registers: IXL, IXH, IYL, IYH),
2197           "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R),
2198           "infc" (instruction IN F,(C) or IN (C)), "outc0" (instruction OUT
2199           (C),0).  Note that rather than extending a basic instruction set,
2200           the extention mnemonics starting with "-" revoke the respective
2201           functionality: "-march=z80-full+xyhl" first removes all default
2202           extentions and adds support for index registers halves only.
2203
2204           If this option is not specified then "-march=z80+xyhl+infc" is
2205           assumed.
2206
2207       -local-prefix=prefix
2208           Mark all labels with specified prefix as local. But such label can
2209           be marked global explicitly in the code. This option do not change
2210           default local label prefix ".L", it is just adds new one.
2211
2212       -colonless
2213           Accept colonless labels. All symbols at line begin are treated as
2214           labels.
2215
2216       -sdcc
2217           Accept assembler code produced by SDCC.
2218
2219       -fp-s=FORMAT
2220           Single precision floating point numbers format. Default: ieee754
2221           (32 bit).
2222
2223       -fp-d=FORMAT
2224           Double precision floating point numbers format. Default: ieee754
2225           (64 bit).
2226

SEE ALSO

2228       gcc(1), ld(1), and the Info entries for binutils and ld.
2229
2231       Copyright (c) 1991-2020 Free Software Foundation, Inc.
2232
2233       Permission is granted to copy, distribute and/or modify this document
2234       under the terms of the GNU Free Documentation License, Version 1.3 or
2235       any later version published by the Free Software Foundation; with no
2236       Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2237       Texts.  A copy of the license is included in the section entitled "GNU
2238       Free Documentation License".
2239
2240
2241
2242binutils-2.35.1                   2021-03-12                             AS(1)
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