1ASIMUT(1) cao-vlsi reference manual ASIMUT(1)
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6 asimut - A simulation tool for hardware descriptions
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11 This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM
12 team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris,
13 France.
14 Web : http://asim.lip6.fr/recherche/alliance/
16 E-mail : alliance-users@asim.lip6.fr
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19 asimut [options] [root_file] [pattern_file] [result_file]
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23 asimut is a logical simulation tool for hardware descriptions. It com‐
24 piles and loads a complete hardware description written in VHDL (Very
25 high speed integrated circuits Hardware Description Language). The
26 hardware description may be structural (a hierarchy of instances) or
27 behavioural. Only a subset of VHDL is supported. Descriptions that do
28 not match this subset cause a syntax error during compilation. See
29 vhdl(5) for detailed information about the supported subset of VHDL.
30 Once a hardware description is loaded, asimut looks for a simulation
33 pattern description file. This file is to be written in pat format.
34 The file is compiled, loaded and linked with the hardware description.
35 Then, the simulation is started. When patterns are processed, a result
36 file in pat format is produced.
37 If a save action has been requested in the pattern description file
40 (see pat (5)), asimut creates also a save file representing the state
41 of the description at the end of the simulation of the last pattern.
42 The save file is named root_file.sav, where root_file is the name of
43 the description.
44 The save file can be used in a later simulation sequence to initialize
47 the state of the (same) hardware description before the simulation
48 begins. Using this mechanism, a large sequence of patterns can be
49 breaked onto several small sequences, each one initializing the hard‐
50 ware description with the save file resulted from the previous
51 sequence.
52 asimut reads several parameters from the environment variables :
55 MBK_CATA_LIB list of directories containing description and pat‐
58 tern files (using $PATH syntax). The default path
59 is the current directory (see mbk(1)).
60 MBK_WORK_LIB specifies the current working directory. The work‐
62 ing directory indicates the place where all output
63 files are written.
64 MBK_CATAL_NAME Indicates the file where the behavioral description
66 files are listed. This file is used to leaf cells
67 of a structural description.(see mbk(1))
68 MBK_IN_LO file extension for structural entity. (see mbk(1))
70 VH_BEHSFX list of file extensions for behavioural entities
72 (using $PATH syntax). The default file extension is
73 vbe.
74 VH_PATSFX list of file extensions for pattern description
76 entities (using $PATH syntax). The default file
77 extension is pat.
78 VH_DLYSFX list of file extensions for delays description
80 entities (using $PATH syntax). The default file
81 extension is dly.
82 VH_MAXERR maximum number of errors allowed during simulation
84 phase. If the number of errors occurred during sim‐
85 ulation reaches VH_MAXERR, asimut stops the simula‐
86 tion at the end of processing the current pattern.
87 Patterns following the current pattern remain
88 unprocessed and are reproduced in the result file.
89 The default value of VH_MAXERR is 10.
90 root_file is the name of the description.
93 By default asimut looks for a structural description. It uses the
96 MBK_IN_LO environment variables to identify both the format and the
97 extension of structural description files. To load structural VHDL
98 files MBK_IN_LO must be set to vst.
99 To load a pure behavioural description -b option must be specified. In
102 such a case asimut loads a data flow VHDL description file. The
103 VH_BEHSFX environment variable gives the extensions to be used.
104 pattern_file is the entity name of the pattern description. The file
107 containing this entity must be named pattern_file.ext , where ext is
108 one of the extension specified in VH_PATSFX.
109 result_file is the result file produced by asimut. The result file is a
112 pattern description file with the extension specified by VH_PATSFX.
113
116 -b consider the root_file description as a behavioural
117 description
118 -backdelay [min, max, typ] delay_file
120 use file delay_file.ext for delays backannotation,
121 where ext is one of the extension specified in
122 VH_DLYSFX.
123 -bdd use BDDs (Binary Decision Diagram) to represent
125 expressions. Using this option makes the simulation
126 be two times faster but increases memory require‐
127 ment
128 -c run only the compilation stage
130 -core core_file at the first error encountered, dump the state of
132 the circuit in both an ascii file (suffixed .cor)
133 and a binary save file (suffixed .sav) which can be
134 used as initialization file in a further session.
135 If the -nores option is specified a pattern file is
136 also produced.
137 -dbg[sbpldc] call the debugger (developer usage)
139 -defaultdelay (-dd) only null delays (no after clause in the VHDL file)
141 are changed if backannotated delays or fixed delays
142 are specified.
143 -fixeddelay value (-fd value)
145 all delays of the description are fixed to value.
146 -h display this help file
148 -i value initialize all signals of the description with
150 value. Value can be 0 or 1
151 -i save_file read a save file and use it to initialize the state
153 of the description before processing the first pat‐
154 tern (the file name cannot be 1 nor 0)
155 -inspect instance_name
157 produce a pattern file corresponding to the inter‐
158 face of the instance identified by instance-name
159 -l n print at most n characters for pattern labels. The
161 default value for n is 15.
162 -nores do not generate result file
164 -p n load at most n patterns from input pattern file
166 each time. Using this feature reduces memory allo‐
167 cation when a great number of patterns are to be
168 simulated. In addition after the n patterns have
169 been processed, the simulation result is printed in
170 the result pattern file. The default value for n is
171 0 which makes the whole pattern file be loaded.
172 -t trace signals when making BDDs (developer usage).
174 -transport use transport delay model (default is inertial).
176 -zerodelay (-zd) all the delays of the VHDL description are supposed
178 to be null delays.
179
182 asimut -b -i init_add adder_32 adder_patterns res_add
183 simulates a behavioural description held in the file named
185 'adder_32.vbe using the pattern file `adder_patterns.pat'. The simula‐
186 tion results is written into 'res_add.pat' and the description is ini‐
187 tialized with the values contained in 'init_add.sav'.
188
191 Register initializations in the pattern file allows changing the value
192 of a register into a known value. However, using this feature to ini‐
193 tialize a register before executing the first pattern is not recom‐
194 mended. Registers value (defined by the initialization statement) may
195 be overwritten since description has not a coherent state before the
196 first pattern.
197
200 vhdl(5), pat(5), genpat(1), mbk(1)
201ASIM/LIP6 October 1, 1997 ASIMUT(1)