1LIBPFM(3) Linux Programmer's Manual LIBPFM(3)
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6 libpfm_intel_hsw - support for Intel Haswell core PMU
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9 #include <perfmon/pfmlib.h>
10 PMU name: hsw
12 PMU desc: Intel Haswell
13 PMU name: hsw_ep
14 PMU desc: Intel Haswell-EP
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18 The library supports the Intel Haswell and Haswell-EP core PMU. It
19 should be noted that this PMU model only covers each core's PMU and not
20 the socket level PMU.
21 On Haswell, the number of generic counters depends on the Hyperthread‐
23 ing (HT) mode. When HT is on, then only 4 generic counters are avail‐
24 able. When HT is off, then 8 generic counters are available. The
25 pfm_get_pmu_info() function returns the maximum number of generic coun‐
26 ters in num_cntrs.
27
30 The following modifiers are supported on Intel Haswell processors:
31 u Measure at user level which includes privilege levels 1, 2, 3.
33 This corresponds to PFM_PLM3. This is a boolean modifier.
34 k Measure at kernel level which includes privilege level 0. This
36 corresponds to PFM_PLM0. This is a boolean modifier.
37 i Invert the meaning of the event. The counter will now count
39 cycles in which the event is not occurring. This is a boolean
40 modifier
41 e Enable edge detection, i.e., count only when there is a state
43 transition from no occurrence of the event to at least one
44 occurrence. This modifier must be combined with a counter mask
45 modifier (m) with a value greater or equal to one. This is a
46 boolean modifier.
47 c Set the counter mask value. The mask acts as a threshold. The
49 counter will count the number of cycles in which the number of
50 occurrences of the event is greater or equal to the threshold.
51 This is an integer modifier with values in the range [0:255].
52 t Measure on both threads at the same time assuming hyper-thread‐
54 ing is enabled. This is a boolean modifier.
55 ldlat Pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY
57 event. This is an integer attribute that must be in the range
58 [3:65535]. It is required for this event. Note that the event
59 must be used with precise sampling (PEBS).
60 intx Monitor the event only when executing inside a transactional
62 memory region (in tx). Event does not count otherwise. This is a
63 boolean modifiers. Default value is 0.
64 intxcp Do not count occurrences of the event when they are inside an
66 aborted transactional memory region. This is a boolean modifier.
67 Default value is 0.
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71 Intel Haswell provides two offcore_response events. They are called
72 OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1.
73 Those events need special treatment in the performance monitoring in‐
75 frastructure because each event uses an extra register to store some
76 settings. Thus, in case multiple offcore_response events are monitored
77 simultaneously, the kernel needs to manage the sharing of that extra
78 register.
79 The offcore_response events are exposed as a normal events by the
81 library. The extra settings are exposed as regular umasks. The library
82 takes care of encoding the events according to the underlying kernel
83 interface.
84 On Intel Haswell, the umasks are divided into three categories:
86 request, supplier and snoop. The user must provide at least one umask
87 for each category. The categories are shown in the umask descriptions.
88 There is also the special response umask called ANY_RESPONSE. When this
90 umask is used then it overrides any supplier and snoop umasks. In other
91 words, users can specify either ANY_RESPONSE OR any combinations of
92 supplier + snoops.
93 In case no supplier or snoop is specified, the library defaults to
95 using ANY_RESPONSE.
96 For instance, the following are valid event selections:
98 OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE
100 OFFCORE_RESPONSE_0:ANY_REQUEST
102 OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY
104 But the following are illegal:
107 OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:ANY_RESPONSE
110 OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY:ANY_RESPONSE
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115 Stephane Eranian <eranian@gmail.com>
116 April, 2013 LIBPFM(3)