Verilog::Netlist::Defparam(3pm)

1Netlist::Defparam(3)  User Contributed Perl Documentation Netlist::Defparam(3)
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NAME

6       Verilog::Netlist::Defparam - Defparam assignment
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SYNOPSIS

9         use Verilog::Netlist;
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11         ...
12         foreach my $cont ($module->statements)
13           print $cont->name;
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DESCRIPTION

16       A Verilog::Netlist::Defparam object is created by Verilog::Netlist for
17       every defparam in the current module.
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ACCESSORS

20       See also Verilog::Netlist::Subclass for additional accessors and
21       methods.
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23       $self->keyword
24           Keyword used to declare the assignment.  Currently "defparam" is
25           the only supported value.
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27       $self->lhs
28           Left hand side of the assignment.
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30       $self->module
31           Pointer to the module the cell is in.
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33       $self->netlist
34           Reference to the Verilog::Netlist the cell is under.
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36       $self->rhs
37           Right hand side of the assignment.
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MEMBER FUNCTIONS

40       See also Verilog::Netlist::Subclass for additional accessors and
41       methods.
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43       $self->dump
44           Prints debugging information for this cell.
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DISTRIBUTION

47       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
48       EDA software tool suite.  The latest version is available from CPAN and
49       from <https://www.veripool.org/verilog-perl>.
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51       Copyright 2000-2021 by Wilson Snyder.  This package is free software;
52       you can redistribute it and/or modify it under the terms of either the
53       GNU Lesser General Public License Version 3 or the Perl Artistic
54       License Version 2.0.
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AUTHORS

57       Wilson Snyder <wsnyder@wsnyder.org>
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