1EXT(5)                        File Formats Manual                       EXT(5)
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NAME

6       ext - format of .ext files produced by Magic's hierarchical extractor
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DESCRIPTION

10       Magic's  extractor produces a .ext file for each cell in a hierarchical
11       design.  The .ext file for cell name is name.ext.  This  file  contains
12       three  kinds  of information: environmental information (scaling, time‐
13       stamps, etc), the extracted circuit corresponding to the mask  geometry
14       of  cell  name,  and the connections between this mask geometry and the
15       subcells of name.
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17       A .ext file consists of a series of lines, each of which begins with  a
18       keyword.   The keyword beginning a line determines how the remainder of
19       the line is interpreted.  The following  set  of  keywords  define  the
20       environmental information:
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22       tech techname
23              Identifies  the  technology of cell name as techname, e.g, nmos,
24              cmos.
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26       timestamp time
27              Identifies the time when cell name was last modified.  The value
28              time  is  the  time stored by Unix, i.e, seconds since 00:00 GMT
29              January 1, 1970.  Note that  this  is  not  the  time  name  was
30              extracted,  but  rather  the  timestamp value stored in the .mag
31              file.  The incremental extractor compares the timestamp in  each
32              .ext  file  with the timestamp in each .mag file in a design; if
33              they differ, that cell is re-extracted.
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35       version version
36              Identifies the version of .ext format used  to  write  name.ext.
37              The current version is 5.1.
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39       style style
40              Identifies the style that the cell has been extracted with.
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42       scale rscale cscale lscale
43              Sets  the  scale  to be used in interpreting resistance, capaci‐
44              tance, and linear dimension values in the remainder of the  .ext
45              file.   Each  resistance  value  must be multiplied by rscale to
46              give the real resistance in milliohms.  Each  capacitance  value
47              must  be  multiplied  by  cscale to give the real capacitance in
48              attofarads.  Each linear dimension (e.g, width,  height,  trans‐
49              form  coordinates) must be multiplied by lscale to give the real
50              linear dimension in centimicrons.   Also,  each  area  dimension
51              (e.g, transistor channel area) must be multiplied by scale*scale
52              to give the real area in square centimicrons.  At most one scale
53              line may appear in a .ext file.  If none appears, all of rscale,
54              cscale, and lscale default to 1.
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56       resistclasses r1 r2 ...
57              Sets the  resistance  per  square  for  the  various  resistance
58              classes  appearing  in  the technology file.  The values r1, r2,
59              etc. are in milliohms; they are  not  scaled  by  the  value  of
60              rscale  specified  in the scale line above.  Each node in a .ext
61              file has a perimeter and area for  each  resistance  class;  the
62              values  r1,  r2,  etc.  are used to convert these perimeters and
63              areas into actual node resistances.  See  ``Magic  Tutorial  #8:
64              Circuit  Extraction''  for  a description of how resistances are
65              computed from perimeters and areas by the program ext2sim.
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67       The following keywords define the circuit formed by the  mask  informa‐
68       tion in cell name.  This circuit is extracted independently of any sub‐
69       cells; its connections to subcells are handled by the keywords  in  the
70       section after this one.
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72       node name R C x y type a1 p1 a2 p2 ... aN pN
73              Defines an electrical node in name.  This node is referred to by
74              the name name in subsequent equiv lines, connections to the ter‐
75              minals of transistors in fet lines, and hierarchical connections
76              or adjustments using merge or adjust.   The  node  has  a  total
77              capacitance  to  ground of C attofarads, and a lumped resistance
78              of R milliohms.  For purposes of going back from the  node  name
79              to  the geometry defining the node, (x,y) is the coordinate of a
80              point inside the node, and type is the layer on which this point
81              appears.  The values a1, p1, ... aN, pN are the area and perime‐
82              ter for the material in each of the resistance classes described
83              by  the  resistclasses  line  at the beginning of the .ext file;
84              these values are used to compute  adjusted  hierarchical  resis‐
85              tances more accurately.  NOTE: since many analysis tools compute
86              transistor gate capacitance  themselves  from  the  transistor's
87              area and perimeter, the capacitance between a node and substrate
88              (GND!) normally does not include the capacitance from transistor
89              gates  connected to that node.  If the .sim file was produced by
90              ext2sim(1), check the technology file that was used  to  produce
91              the  original  .ext files to see whether transistor gate capaci‐
92              tance is included or excluded; see ``Magic  Maintainer's  Manual
93              #2: The Technology File'' for details.
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95       attr name xl yl xh yh type text
96              One  of these lines appears for each label ending in the charac‐
97              ter ``@'' that was attached to geometry in the node  name.   The
98              location  of  each attribute label (xl yl xh yh) and the type of
99              material to which it was attached (type) are  given  along  with
100              the text of the label minus the trailing ``@'' character (text).
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102       equiv node1 node2
103              Defines  two  node names in cell name as being equivalent: node1
104              and node2.  In a collection  of  node  names  related  by  equiv
105              lines,  exactly  one  must  be  defined by a node line described
106              above.
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108       fet type xl yl xh yh area perim sub GATE T1 T2 ...
109              Defines a transistor in name.  The kind of transistor is type, a
110              string  that  comes  from the technology file and is intended to
111              have meaning to  simulation  programs.   The  coordinates  of  a
112              square  entirely  contained in the gate region of the transistor
113              are (xl, yl) for its lower-left  and  (xh, yh)  for  its  upper-
114              right.  All four coordinates are in the name's coordinate space,
115              and are subject to scaling as described  in  scale  above.   The
116              gate  region of the transistor has area area square centimicrons
117              and perimeter perim centimicrons.  The substrate of the transis‐
118              tor is connected to node sub.
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120              The  remainder  of  a  fet line consists of a series of triples:
121              GATE, T1, ....  Each describes one of the terminals of the tran‐
122              sistor; the first describes the gate, and the remainder describe
123              the transistor's non-gate terminals  (e.g,  source  and  drain).
124              Each  triple  consists  of the name of a node connecting to that
125              terminal, a terminal length, and an attribute list.  The  termi‐
126              nal  length is in centimicrons; it is the length of that segment
127              of the channel perimeter connecting to adjacent  material,  such
128              as polysilicon for the gate or diffusion for a source or drain.
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130              The  attribute list is either the single token ``0'', meaning no
131              attributes, or a comma-separated list of strings.   The  strings
132              in  the attribute list come from labels attached to the transis‐
133              tor.  Any label ending in the character ``^''  is  considered  a
134              gate  attribute  and appears on the gate's attribute list, minus
135              the trailing ``^''.  Gate attributes may lie  either  along  the
136              border of a channel or in its interior.  Any label ending in the
137              character ``$'' is considered a non-gate attribute.  It  appears
138              on  the list of the terminal along which it lies, also minus the
139              trailing ``$''.  Non-gate attributes may only lie on the  border
140              of the channel.
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142       The keywords in this section describe information that is not processed
143       hierarchically: path lengths and accurate resistances that are computed
144       by  flattening  an entire node and then producing a value for the flat‐
145       tened node.
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147       killnode node
148              During resistance extraction, it is sometimes necessary to break
149              a  node  up  into  several  smaller  nodes.  The appearance of a
150              killnode line during the processing of a .ext  file  means  that
151              all information currently accumulated about node, along with all
152              fets that have a terminal connected to node,  should  be  thrown
153              out;  it will be replaced by information later in the .ext file.
154              The order of processing .ext files is  important  in  order  for
155              this  to work properly: children are processed before their par‐
156              ents, so a killnode in a parent overrides one in a child.
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158       resist node1 node2 R
159              Defines a resistor of R milliohms between the  two  nodes  node1
160              and node2.  Both names are hierarchical.
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162       distance name1 name2 dmin dmax
163              Gives  the  distance  between  two electrical terminals name1 (a
164              driver) and name2 (a receiver).  Note that these  are  terminals
165              and  not  nodes:  the names (which are hierarchical label names)
166              are used to specify two different locations on the same electri‐
167              cal node.  The two distances, dmin and dmax, are the lengths (in
168              lambda) of the shortest and longest acyclic  paths  between  the
169              driver and receiver.
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171       The  keywords  in this last section describe the subcells used by name,
172       and how connections are made to and between them.
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174       use def use-id TRANSFORM
175              Specifies that cell def with instance  identifier  use-id  is  a
176              subcell  of cell name.  If cell def is arrayed, then use-id will
177              be followed by two  bracketed  subscript  ranges  of  the  form:
178              [lo,hi,sep].   The  first  range is for x, and the second for y.
179              The subscripts for a given dimension are lo  through  hi  inclu‐
180              sive,  and the separation between adjacent array elements is sep
181              centimicrons.
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183              TRANSFORM is a set of six integers that describe how coordinates
184              in  def are to be transformed to coordinates in the parent name.
185              It is used by ext2sim(1) in transforming transistor locations to
186              coordinates in the root of a design.  The six integers of TRANS‐
187              FORM (ta, tb, tc, td, te, tf) are interpreted as  components  in
188              the following transformation matrix, by which all coordinates in
189              def are post-multiplied to get coordinates in name:
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191                                  ta   td   0
192                                  tb   te   0
193                                  tc   tf   1
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195       merge path1 path2 C a1 p1 a2 p2  ... aN pN
196              Used to specify a connection between two subcells, or between  a
197              subcell  and mask information of name.  Both path1 and path2 are
198              hierarchical node names.  To  refer  to  a  node  in  cell  name
199              itself,  its pathname is just its node name.  To refer to a node
200              in a subcell of name, its pathname consists of the use-id of the
201              subcell  (as  it  appeared  in  a use line above), followed by a
202              slash (/), followed by the node name in the subcell.  For  exam‐
203              ple,  if  name  contains subcell sub with use identifier sub-id,
204              and sub contains node n, the full pathname of node n relative to
205              name will be sub-id/n.
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207       Connections between adjacent elements of an array are represented using
208       a special syntax that takes advantage of the regularity of  arrays.   A
209       use-id  in  a  path  may  optionally be followed by a range of the form
210       [lo:hi] (before the following slash).  Such a use-id is interpreted  as
211       the  elements  lo  through hi inclusive of a one-dimensional array.  An
212       element of a two-dimensional array may be  subscripted  with  two  such
213       ranges: first the y range, then the x range.
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215       Whenever  one path in a merge line contains such a subscript range, the
216       other must contain one of comparable size.  For example,
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218                 merge  sub-id[1:4,2:8]/a  sub-id[2:5,1:7]/b
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220       is acceptable because the range 1:4 is the same size as  2:5,  and  the
221       range 2:8 is the same size as 1:7.
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223       When  a  connection  occurs between nodes in different cells, it may be
224       that some resistance and capacitance  has  been  recorded  redundantly.
225       For  example,  polysilicon  in  one  cell  may  overlap  polysilicon in
226       another, so the capacitance to substrate will have been recorded twice.
227       The  values C, a1, p1, etc. in a merge line provide a way of compensat‐
228       ing for such overlap.  Each of a1,  p1,  etc.  (usually  negative)  are
229       added  to  the area and perimeter for material of each resistance class
230       to give an adjusted area and perimeter for  the  aggregate  node.   The
231       value  C  attofarads (also usually negative) is added to the sum of the
232       capacitances (to substrate) of nodes path1 and path2 to give the capac‐
233       itance of the aggregate node.
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235       cap node1 node2 C
236              Defines  a  capacitor  between  the  nodes node1 and node2, with
237              capacitance C.  This construct is used to specify  both  intern‐
238              odal capacitance within a single cell and between cells.
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AUTHOR

242       Walter Scott
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SEE ALSO

246       ext2sim(1), magic(1)
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2504th Berkeley Distribution                                               EXT(5)
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