fsm(5alc)

1FSM(5)              VHDL subset of ASIM/LIP6/CAO-VLSI lab.              FSM(5)
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NAME

6       fsm - Alliance VHDL Finite State Machine description subset.
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DESCRIPTION

10       This  document  describes  the  Alliance  VHDL  subset for Finite State
11       Machine description.
12
13       This FSM subset is neither accepted by the logic  simulator  asimut(1),
14       nor the formal prover proof(1).
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16       This  VHDL  subset is defined to enable classical MOORE and MEALEY syn‐
17       chronous finite state machine description as well as stack FSM descrip‐
18       tion (see syf(1) for further information about this kind of FSM).
19       A  FSM  description  is made of two and only two processes.  Connectors
20       and signals can only be of in, out, and  two  user  defined  enumerated
21       types.  Vectors of in and out types are also allowed.
22       FSM's  states  and stack control signals must be declared as enumerated
23       type.
24       For the scan-path, three more signals are required :
25              - scan_test: in bit
26              - scan_in: in bit
27              - scan_out: out bit
28       For a ROM implementation, the vdd and vss signals  must  be  explicitly
29       declared as :
30              - rom_vdd : in bit
31              - rom_vss : in bit
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These signals, declared in the interface, are not used or assigned in the FSM

34       description.
35       The '-P' option of syf(1) allows scan-path implementation.
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37       Pragmas :
38              A pragma is a comment that gives necessary  information  to  the
39              synthesis and formal proof tools.
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41              Three pragmas are used, their generic names are :
42                     - CLOCK : External clock signal name.
43                     - CURRENT_STATE : Current State name.
44                     - NEXT_STATE : Next State name.
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Ten other pragmas are optional.

47       Three pragmas are required only for scan-path implementation.
48              - SCAN_TEST : Enable test mode (scan-path).
49              - SCAN_IN : scan-path input.
50              - SCAN_OUT : scan-path output.
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Five others are used only in a STACK FSM.

53              - RETURN_STATE : Return State name.
54              - CONTROL : Stack Control signal name.
55              - POP : POP operation on the stack.
56              - PUSH : PUSH operation on the stack.
57              - NOP : NOP operation on the stack.
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The last ones for ROM implementation

60              - ROM_VDD : Name of the vdd signal of the ROM.
61              - ROM_VSS :Name of the vss signal of the ROM.
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65       Two  different  processes  are  used  : The first process, called state
66       process,
67       allows to describe state transition and outputs generation.  It is  not
68       controlled by the clock.  The second process is controlled by the clock
69       and describes the state register and stack registers modifications.
70       State process sensitivity list contains inputs  and  CURRENT_STATE,  it
71       means  that the state process is activated when the CURRENT_STATE or an
72       input signal changes.  A case statement is used to describe,  for  each
73       state, the next state and outputs.
74       The  second process sensitivity list contains the clock signal, so this
75       process is  enabled  whenever  clock  changes.   Both  Level  sensitive
76       latches,  and edge triggered flip flops can be used for state registers
77       and stack implementation.
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EXAMPLE

80       Entity FSM_EX is
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82       port(
83          ck    : in bit ;
84          reset :in bit;
85          t_mode:in bit;
86          s_in  :in bit;
87          i     :in bit;
88          s_out :out bit;
89          o     :out bit
90       );
91       End FSM_EX;
92
93       architecture auto of FSM_EX is
94
95       type STATE_TYPE is (S0,S1,S2,S3,S4,S5);
96       type CONTROL is (PUSH,POP,NOP);
97
98       -- pragma CLOCK ck
99       -- pragma CURRENT_STATE CURRENT_STATE
100       -- pragma NEXT_STATE NEXT_STATE
101       -- pragma RETURN_STATE RETURN_STATE
102       -- pragma CONTROL CTRL
103       -- pragma PUSH PUSH
104       -- pragma POP POP
105       -- pragma NOP NOP
106       -- pragma SCAN_TEST t_mode
107       -- pragma SCAN_IN s_in
108       -- pragma SCAN_OUT s_out
109
110       signal CURRENT_STATE, NEXT_STATE, RETURN_STATE : STATE_TYPE;
111       signal CTRL : CONTROL;
112       signal STACK_0, STACK_1 : STATE_TYPE ;
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114
115       begin
116
117       PROCESS(CURRENT_STATE,I,reset)
118         begin
119           if(reset) then
120             NEXT_STATE <= S0 ;
121             o <= '0' ;
122         else
123             case CURRENT_STATE is
124               WHEN S0 =>
125               NEXT_STATE <= S1;
126               RETURN_STATE <= S5;
127               CTRL <= PUSH;
128
129               o <= '0';
130
131               WHEN S1 =>
132               if (I = '1') then
133                 NEXT_STATE <= S2;
134                 CTRL <= NOP;
135               else
136                 NEXT_STATE <= S3;
137                 CTRL <= NOP;
138               end if;
139
140               o <= '0';
141
142               WHEN S2 =>
143               NEXT_STATE <= S4;
144               CTRL <= NOP;
145
146               o <= '0';
147
148               WHEN S3 =>
149               NEXT_STATE <= S4;
150               CTRL <= NOP;
151
152               o <= '0';
153
154               WHEN S4 =>
155               NEXT_STATE <= STACK_0;
156               CTRL <= POP;
157
158               o <= '1';
159
160               WHEN S5 =>
161               if (I = '1') then
162                 NEXT_STATE <= S1;
163                 RETURN_STATE <= S0 ;
164                 CTRL <= PUSH;
165               else
166                 NEXT_STATE <= S5;
167                 CTRL <= NOP;
168               end if ;
169
170               o <= '0';
171
172              WHEN others =>
173               assert ('1')
174               report "illegal state";
175
176           end case;
177         end if ;
178       end process;
179
180       process(ck)
181         begin
182           if(ck = '0' and not ck' stable) then
183             CURRENT_STATE <= NEXT_STATE;
184             case CTRL is
185               WHEN POP =>
186                 STACK_0 <= STACK_1;
187
188               WHEN PUSH =>
189                 STACK_1 <= STACK_0;
190                 STACK_0 <= RETURN_STATE;
191               WHEN NOP =>
192                 NULL;
193             end case;
194           end if;
195       end process;
196
197       end auto;
198
199

MULTI FSM EXAMPLE

201       It is possible to describe in the same description two or more FSM com‐
202       municating  each  others  throw internal signals as shown below.  It is
203       also possible to incorporate concurrent statements  using  VBE(5)  VHDL
204       coding style.
205
206       ENTITY multi_fsm is
207       PORT
208       ( ck       : in  BIT;
209         data_in  : in  BIT;
210         reset    : in  BIT;
211         data_out : out BIT
212       );
213       END multi_fsm;
214
215
216       ARCHITECTURE FSM OF multi_fsm is
217
218          TYPE A_ETAT_TYPE IS (A_E0, A_E1);
219          SIGNAL A_NS, A_CS : A_ETAT_TYPE;
220
221          TYPE B_ETAT_TYPE IS (B_E0, B_E1);
222          SIGNAL B_NS, B_CS : B_ETAT_TYPE;
223
224       --PRAGMA CURRENT_STATE A_CS  FSM_A
225       --PRAGMA NEXT_STATE A_NS     FSM_A
226       --PRAGMA CLOCK ck            FSM_A
227       --PRAGMA FIRST_STATE A_E0    FSM_A
228
229       --PRAGMA CURRENT_STATE B_CS  FSM_B
230       --PRAGMA NEXT_STATE B_NS     FSM_B
231       --PRAGMA CLOCK ck            FSM_B
232       --PRAGMA FIRST_STATE B_E0    FSM_B
233
234          SIGNAL ACK, REQ, DATA_INT : BIT;
235
236       BEGIN
237
238       A_1 : PROCESS ( A_CS, ACK )
239       BEGIN
240         IF ( reset = '1' )
241         THEN A_NS     <= A_E0;
242              DATA_OUT <= '0';
243              REQ      <= '0';
244         ELSE
245         CASE A_CS is
246           WHEN A_E0 =>
247             IF ( ACK ='1') THEN A_NS <= A_E1;
248                            ELSE A_NS <= A_E0;
249             END IF;
250             DATA_OUT <= '0';
251             REQ      <= '1';
252           WHEN A_E1 =>
253             IF ( ACK ='1') THEN A_NS <= A_E1;
254                            ELSE A_NS <= A_E0;
255             END IF;
256             DATA_OUT <= DATA_INT;
257             REQ      <= '0';
258         END CASE;
259         END IF;
260       END PROCESS A_1;
261
262       A_2 : PROCESS( ck )
263       BEGIN
264           IF ( ck = '1' AND NOT ck'STABLE )
265           THEN A_CS <= A_NS;
266           END IF;
267       END PROCESS A_2;
268
269       -------
270
271       B_1 : PROCESS ( B_CS, ACK )
272       BEGIN
273         IF ( reset = '1' )
274         THEN B_NS     <= B_E0;
275              DATA_INT <= '0';
276              ACK      <= '0';
277         ELSE
278         CASE B_CS is
279           WHEN B_E0 =>
280             IF ( REQ ='1') THEN B_NS <= B_E1;
281                            ELSE B_NS <= B_E0;
282             END IF;
283             DATA_INT <= '0';
284             ACK      <= '0';
285           WHEN B_E1 =>
286             IF ( REQ ='1') THEN B_NS <= B_E1;
287                            ELSE B_NS <= B_E0;
288             END IF;
289             DATA_INT <= DATA_IN;
290             ACK      <= '1';
291         END CASE;
292         END IF;
293       END PROCESS B_1;
294
295       B_2 : PROCESS( ck )
296       BEGIN
297           IF ( ck = '1' AND NOT ck'STABLE )
298           THEN B_CS <= B_NS;
299           END IF;
300       END PROCESS B_2;
301
302       END FSM;
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