1LIBPFM(3)                  Linux Programmer's Manual                 LIBPFM(3)
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NAME

6       libpfm_intel_tmt - support for Intel Tremont core PMU
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SYNOPSIS

9       #include <perfmon/pfmlib.h>
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11       PMU name: tmt
12       PMU desc: Intel Tremont
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DESCRIPTION

16       The library supports the Intel Tremont core PMU.
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MODIFIERS

20       The following modifiers are supported on Intel Tremont processors:
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22       u      Measure  at  user level which includes privilege levels 1, 2, 3.
23              This corresponds to PFM_PLM3.  This is a boolean modifier.
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25       k      Measure at kernel level which includes privilege level  0.  This
26              corresponds to PFM_PLM0.  This is a boolean modifier.
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28       i      Invert  the meaning of the event. The counter will now count cy‐
29              cles in which the event is not occurring. This is a boolean mod‐
30              ifier
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32       e      Enable  edge  detection,  i.e., count only when there is a state
33              transition from no occurrence of the event to at least  one  oc‐
34              currence.  This  modifier  must  be combined with a counter mask
35              modifier (m) with a value greater or equal to one.   This  is  a
36              boolean modifier.
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38       c      Set  the  counter  mask value. The mask acts as a threshold. The
39              counter will count the number of cycles in which the  number  of
40              occurrences  of  the event is greater or equal to the threshold.
41              This is an integer modifier with values in the range [0:255].
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OFFCORE_RESPONSE events

45       Intel Tremont provides two offcore_response events:  OFFCORE_RESPONSE_0
46       and  OFFCORE_RESPONSE_1.  The   OCR  event  is  aliased  to OFFCORE_RE‐
47       SPONSE_0.
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49       Those events need special treatment in the performance  monitoring  in‐
50       frastructure  because  each  event uses an extra register to store some
51       settings. Thus, in case multiple offcore_response events are  monitored
52       simultaneously,  the  kernel  needs to manage the sharing of that extra
53       register.
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55       The offcore_response event is exposed as a normal event by the library.
56       The  extra  settings  are  exposed as regular umasks. The library takes
57       care of encoding the events according for the underlying kernel  inter‐
58       face.
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60       On  Intel Tremont, it is not possible to combine the request, supplier,
61       snoop, fields anymore to  avoid  invalid  combinations.  As  such,  the
62       umasks  provided  by  the library are the only ones supported and vali‐
63       dated.
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AUTHORS

67       Stephane Eranian <eranian@gmail.com>
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71                                  March, 2020                        LIBPFM(3)
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