Verilog::Netlist(3pm)

1Netlist(3)            User Contributed Perl Documentation           Netlist(3)
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NAME

6       Verilog::Netlist - Verilog Netlist
7

SYNOPSIS

9           use Verilog::Netlist;
10
11           # Setup options so files can be found
12           use Verilog::Getopt;
13           my $opt = new Verilog::Getopt;
14           $opt->parameter( "+incdir+verilog",
15                            "-y","verilog",
16                            );
17
18           # Prepare netlist
19           my $nl = new Verilog::Netlist(options => $opt,);
20           foreach my $file ('testnetlist.v') {
21               $nl->read_file(filename=>$file);
22           }
23           # Read in any sub-modules
24           $nl->link();
25           #$nl->lint();  # Optional, see docs; probably not wanted
26           $nl->exit_if_error();
27
28           foreach my $mod ($nl->top_modules_sorted) {
29               show_hier($mod, "  ", "", "");
30           }
31
32           sub show_hier {
33               my $mod = shift;
34               my $indent = shift;
35               my $hier = shift;
36               my $cellname = shift;
37               if (!$cellname) {$hier = $mod->name;} #top modules get the design name
38               else {$hier .= ".$cellname";} #append the cellname
39               printf("%-45s %s\n", $indent."Module ".$mod->name,$hier);
40               foreach my $sig ($mod->ports_sorted) {
41                   printf($indent."      %sput %s\n", $sig->direction, $sig->name);
42               }
43               foreach my $cell ($mod->cells_sorted) {
44                   printf($indent. "    Cell %s\n", $cell->name);
45                   foreach my $pin ($cell->pins_sorted) {
46                       printf($indent."     .%s(%s)\n", $pin->name, $pin->netname);
47                   }
48                   show_hier($cell->submod, $indent."   ", $hier, $cell->name) if $cell->submod;
49               }
50           }
51

DESCRIPTION

53       Verilog::Netlist reads and holds interconnect information about a whole
54       design database.
55
56       See the "Which Package" section of Verilog::Language if you are unsure
57       which parsing package to use for a new application.
58
59       A Verilog::Netlist is composed of files, which contain the text read
60       from each file.
61
62       A file may contain modules, which are individual blocks that can be
63       instantiated (designs, in Synopsys terminology.)
64
65       Modules have ports, which are the interconnection between nets in that
66       module and the outside world.  Modules also have nets, (aka signals),
67       which interconnect the logic inside that module.
68
69       Modules can also instantiate other modules.  The instantiation of a
70       module is a Cell.  Cells have pins that interconnect the referenced
71       module's pin to a net in the module doing the instantiation.
72
73       Each of these types, files, modules, ports, nets, cells and pins have a
74       class.  For example Verilog::Netlist::Cell has the list of
75       Verilog::Netlist::Pin(s) that interconnect that cell.
76

FUNCTIONS

78       See also Verilog::Netlist::Subclass for additional accessors and
79       methods.
80
81       $netlist->lint
82           Error checks the entire netlist structure.  Currently there are
83           only two checks, that modules are bound to instantiations (which is
84           also checked by $netlist->link), and that signals aren't multiply
85           driven.  Note that as there is no elaboration you may get false
86           errors about multiple drivers from generate statements that are
87           mutually exclusive.  For this reason and the few lint checks you
88           may not want to use this method.  Alternatively to avoid pin
89           interconnect checks, set the $netlist->new (...use_vars=>0...)
90           option.
91
92       $netlist->link()
93           Resolves references between the different modules.
94
95           If link_read=>1 is passed when netlist->new is called (it is by
96           default), undefined modules will be searched for using the
97           Verilog::Getopt package, passed by a reference in the creation of
98           the netlist.  To suppress errors in any missing references, set
99           link_read_nonfatal=>1 also.
100
101       $netlist->new
102           Creates a new netlist structure.  Pass optional parameters by name,
103           with the following parameters:
104
105           implicit_wires_ok => $true_or_false
106                   Indicates whether to allow undeclared wires to be used.
107
108           include_open_nonfatal => $true_or_false
109                   Indicates that include files that do not exist should be
110                   ignored.
111
112           keep_comments => $true_or_false
113                   Indicates that comment fields should be preserved and on
114                   net declarations into the Vtest::Netlist::Net structures.
115                   Otherwise all comments are stripped for speed.
116
117           link_read => $true_or_false
118                   Indicates whether or not the parser should automatically
119                   search for undefined modules through the "options" object.
120
121           link_read_nonfatal => $true_or_false
122                   Indicates that modules that referenced but not found should
123                   be ignored, rather than causing an error message.
124
125           logger => object
126                   Specify a message handler object to be used for error
127                   handling, this class should be a Verilog::Netlist::Logger
128                   object, or derived from one.  If unspecified, a
129                   Verilog::Netlist::Logger local to this netlist will be
130                   used.
131
132           options => $opt_object
133                   An optional pointer to a Verilog::Getopt object, to be used
134                   for locating files.
135
136           parser => $package_name
137                   The name of the parser class. Defaults to
138                   "Verilog::Netlist::File::Parser".
139
140           preproc => $package_name
141                   The name of the preprocessor class. Defaults to
142                   "Verilog::Preproc".
143
144           synthesis => $true_or_false
145                   With synthesis set, define SYNTHESIS, and ignore text
146                   between "ambit", "pragma", "synopsys" or "synthesis"
147                   translate_off and translate_on meta comments.  Note using
148                   metacomments is discouraged as they have led to silicon
149                   bugs (versus ifdef SYNTHESIS); see
150                   <https://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf>.
151
152           use_pinselects => $true_or_false
153                   Indicates that bit selects should be parsed and
154                   interpreted.  False for backward compatibility, but true
155                   recommended in new applications.
156
157           use_vars => $true_or_false
158                   Indicates that signals, variables, and pin interconnect
159                   information is needed; set by default.  If clear do not
160                   read it, nor report lint related pin warnings, which can
161                   greatly improve performance.
162
163       $netlist->dump
164           Prints debugging information for the entire netlist structure.
165

INTERFACE FUNCTIONS

167       $netlist->find_interface($name)
168           Returns Verilog::Netlist::Interface matching given name.
169
170       $netlist->interfaces
171           Returns list of Verilog::Netlist::Interface.
172
173       $netlist->interfaces_sorted
174           Returns name sorted list of Verilog::Netlist::Interface.
175
176       $netlist->new_interface
177           Creates a new Verilog::Netlist::Interface.
178

MODULE FUNCTIONS

180       $netlist->find_module($name)
181           Returns Verilog::Netlist::Module matching given name.
182
183       $netlist->modules
184           Returns list of Verilog::Netlist::Module.
185
186       $netlist->modules_sorted
187           Returns name sorted list of Verilog::Netlist::Module.
188
189       $netlist->modules_sorted_level
190           Returns level sorted list of Verilog::Netlist::Module.  Leaf
191           modules will be first, the top most module will be last.
192
193       $netlist->new_module
194           Creates a new Verilog::Netlist::Module.
195
196       $netlist->new_root_module
197           Creates a new Verilog::Netlist::Module for $root, if one doesn't
198           already exist.
199
200       $netlist->top_modules_sorted
201           Returns name sorted list of Verilog::Netlist::Module, only for
202           those modules which have no children and are not unused library
203           cells.
204

FILE FUNCTIONS

206       $netlist->dependency_write(filename)
207           Writes a dependency file for make, listing all input and output
208           files.
209
210       $netlist->defvalue_nowarn(define)
211           Return the value of the specified define or undef.
212
213       $netlist->dependency_in(filename)
214           Adds an additional input dependency for dependency_write.
215
216       $netlist->dependency_out(filename)
217           Adds an additional output dependency for dependency_write.
218
219       $netlist->delete
220           Delete the netlist, reclaim memory.  Unfortunately netlists will
221           not disappear simply with normal garbage collection from leaving of
222           scope due to complications with reference counting and weaking
223           Class::Struct structures; solutions welcome.
224
225       $netlist->files
226           Returns list of Verilog::Netlist::File.
227
228       $netlist->files_sorted
229           Returns a name sorted list of Verilog::Netlist::File.
230
231       $netlist->find_file($name)
232           Returns Verilog::Netlist::File matching given name.
233
234       $netlist->read_file( filename=>$name)
235           Reads the given Verilog file, and returns a Verilog::Netlist::File
236           reference.
237
238           Generally called as $netlist->read_file.  Pass a hash of
239           parameters.  Reads the filename=> parameter, parsing all
240           instantiations, ports, and signals, and creating
241           Verilog::Netlist::Module structures.
242
243       $netlist->read_libraries()
244           Read any libraries specified in the options=> argument passed with
245           the netlist constructor.  Automatically invoked when netlist
246           linking results in a module that wasn't found, and thus might be
247           inside the libraries.
248
249       $netlist->remove_defines(string)
250           Expand any `defines in the string and return the results.
251           Undefined defines will remain in the returned string.
252
253       $netlist->resolve_filename(string, [lookup_type])
254           Convert a module name to a filename.  Optional lookup_type is
255           'module', 'include', or 'all', to use only module_dirs, incdirs, or
256           both for the lookup.  Return undef if not found.
257
258       $self->verilog_text
259           Returns verilog code which represents the netlist.  The netlist
260           must be already ->link'ed for this to work correctly.
261

BUGS

263       Cell instantiations without any arguments are not supported, a empty
264       set of parenthesis are required.  (Use "cell cell();", not "cell
265       cell;".)
266
267       Order based pin interconnect is not supported, use name based
268       connections.
269

DISTRIBUTION

271       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
272       EDA software tool suite.  The latest version is available from CPAN and
273       from <https://www.veripool.org/verilog-perl>.
274
275       Copyright 2000-2021 by Wilson Snyder.  This package is free software;
276       you can redistribute it and/or modify it under the terms of either the
277       GNU Lesser General Public License Version 3 or the Perl Artistic
278       License Version 2.0.
279

AUTHORS

281       Wilson Snyder <wsnyder@wsnyder.org>
282