1LAX(5) CAO-VLSI Reference Manual LAX(5)
2
6 lax - Parameter file for logic synthesis
7
11 filename.lax
12
15 The .lax file contains user modifiable parameters that lead to differ‐
16 ent logic synthesis.
17
20 Circuit Interfce
21 -- Entity Declaration
24 ENTITY digia IS
26 PORT (
27 clock : in BIT; -- clock
28 jour : in BIT; -- jour
29 reset : in BIT; -- reset
30 vdd : in BIT; -- vdd
31 vss : in BIT; -- vss
32 i : in bit_vector(3 DOWNTO 0) ; -- i
33 porte : out BIT; -- porte
34 alarm : out BIT; -- alarm
35 ep_0 : out BIT; -- ep_0
36 ep_1 : out BIT; -- ep_1
37 ep_2 : out BIT; -- ep_2
38 ep_3 : out BIT; -- ep_3
39 ep_4 : out BIT; -- ep_4
40 ep_5 : out BIT; -- ep_5
41 ep_a : out BIT -- ep_a
42 );
43 END digia;
44 -- Architecture Declaration
47 ARCHITECTURE behaviour_data_flow OF digia IS
49 SIGNAL cs : REG_VECTOR(0 TO 2) REGISTER; -- cs
50 SIGNAL cs_ea : BIT; -- cs_ea
51 SIGNAL ef_ea : BIT; -- ef_ea
52 SIGNAL cs_e5 : BIT; -- cs_e5
53 SIGNAL ef_e5 : BIT; -- ef_e5
54 SIGNAL cs_e4 : BIT; -- cs_e4
55 SIGNAL ef_e4 : BIT; -- ef_e4
56 SIGNAL cs_e3 : BIT; -- cs_e3
57 SIGNAL ef_e3 : BIT; -- ef_e3
58 SIGNAL cs_e2 : BIT; -- cs_e2
59 SIGNAL ef_e2 : BIT; -- ef_e2
60 SIGNAL cs_e1 : BIT; -- cs_e1
61 SIGNAL ef_e1 : BIT; -- ef_e1
62 SIGNAL cs_e0 : BIT; -- cs_e0
63 SIGNAL ef_e0 : BIT; -- ef_e0
64 SIGNAL ef : BIT_VECTOR(0 TO 2); -- ef
65 .Lax parameter file
68 ## This line is a comment
72 ## Set the Optimisation Mode (0..4)
74 ## 0 : full area optimisation
75 ## 2 : 50% area, 50% delay
76 ## 4 : full delay optimisation
77 ## Used by boog and loon
78 #M{4}
79 ## Set the Optimisation Level (1..5)
82 ## 1 : poor optimisation - small computation time
83 ## 5 : best optimisation - long computation time
84 #L{5}
85 ## External Input Delay (in ns)
88 ## Those signals are taken into account to optimise
89 ## the global delay of the circuit.
90 ## Used by boog and loon
91 #D{
92 i(3):300;
93 i(0):100;
94 jour:120;
95 }
96 ## Set the list of early outputs
99 ## Some outputs may be critical. They can be
100 ## optimized in delay before others regardless
101 ## of the optimisation mode.
102 #E{
103 porte;
104 ep_3;
105 }
106 ## Set the list of auxiliary (intermediate) signals to keep
109 ## This can be used to decrease the memory consuption
110 ## when trying to reorder Bdds. Those signals won't
111 ## be reordered.
112 #S{
113 cs_ea;
114 ef_0;
115 ef_1;
116 ef_e4;
117 }
118 ## The following parameters are used for whith glop
120 ## (Delayed --#D--inputs are also used)
121 ## Fanout factor : the max fanout of the
123 ## output connector is multiplied by this factor
124 #T{1000}
125 ## Input Capacitance : The primary inputs of the circuit
127 ## can have fanout values. (in fF)
128 #F{
129 jour:50;
130 }
131 ## External Output Capacitance (in fF)
133 ## Used by boog and loon
134 #C{
135 porte:50;
136 }
137 ## External Input Impedance (in Ohms)
139 ## Used by boog and loon
140 #I{
141 jour:5000;
142 }
143 ## Buffered Input : this is a list of primary inputs whith
145 ## the number of buffer you want to add.
146 #B{
147 clock:1;
148 }
149
153 boom(1), boog(1). loon(1).
154ASIM/LIP6 October 1, 1997 LAX(5)