1LLI(1)                               LLVM                               LLI(1)
2
3
4

NAME

6       lli - directly execute programs from LLVM bitcode
7

SYNOPSIS

9       lli [options] [filename] [program args]
10

DESCRIPTION

12       lli directly executes programs in LLVM bitcode format.  It takes a pro‐
13       gram in LLVM bitcode format and executes it using a  just-in-time  com‐
14       piler or an interpreter.
15
16       lli  is  not an emulator. It will not execute IR of different architec‐
17       tures and it can only interpret (or JIT-compile) for the host architec‐
18       ture.
19
20       The JIT compiler takes the same arguments as other tools, like llc, but
21       they don't necessarily work for the interpreter.
22
23       If filename is not specified, then lli reads the LLVM bitcode  for  the
24       program from standard input.
25
26       The  optional args specified on the command line are passed to the pro‐
27       gram as arguments.
28

GENERAL OPTIONS

30       -fake-argv0=executable
31              Override the argv[0] value passed into the executing program.
32
33       -force-interpreter={false,true}
34              If set to true, use the interpreter even if a just-in-time  com‐
35              piler is available for this architecture. Defaults to false.
36
37       -help  Print a summary of command line options.
38
39       -load=pluginfilename
40              Causes  lli to load the plugin (shared object) named pluginfile‐
41              name and use it for optimization.
42
43       -stats Print statistics from the code-generation passes. This  is  only
44              meaningful for the just-in-time compiler, at present.
45
46       -time-passes
47              Record  the  amount of time needed for each code-generation pass
48              and print it to standard error.
49
50       -version
51              Print out the version of lli and  exit  without  doing  anything
52              else.
53

TARGET OPTIONS

55       -mtriple=target triple
56              Override  the  target triple specified in the input bitcode file
57              with the specified string.  This may result in a  crash  if  you
58              pick  an  architecture  which is not compatible with the current
59              system.
60
61       -march=arch
62              Specify the architecture for which to generate  assembly,  over‐
63              riding  the  target encoded in the bitcode file.  See the output
64              of llc -help for a list of valid architectures.  By default this
65              is  inferred  from the target triple or autodetected to the cur‐
66              rent architecture.
67
68       -mcpu=cpuname
69              Specify a specific chip in the current architecture to  generate
70              code  for.   By  default this is inferred from the target triple
71              and autodetected to the current architecture.   For  a  list  of
72              available  CPUs,  use:  llvm-as  <  /dev/null  |  llc -march=xyz
73              -mcpu=help
74
75       -mattr=a1,+a2,-a3,...
76              Override or control specific attributes of the target,  such  as
77              whether  SIMD operations are enabled or not.  The default set of
78              attributes is set by the current CPU.  For a list  of  available
79              attributes,   use:   llvm-as   <   /dev/null  |  llc  -march=xyz
80              -mattr=help
81

FLOATING POINT OPTIONS

83       -disable-excess-fp-precision
84              Disable optimizations that may increase  floating  point  preci‐
85              sion.
86
87       -enable-no-infs-fp-math
88              Enable optimizations that assume no Inf values.
89
90       -enable-no-nans-fp-math
91              Enable optimizations that assume no NAN values.
92
93       -enable-unsafe-fp-math
94              Causes  lli  to  enable optimizations that may decrease floating
95              point precision.
96
97       -soft-float
98              Causes lli to generate software floating point library calls in‐
99              stead of equivalent hardware instructions.
100

CODE GENERATION OPTIONS

102       -code-model=model
103              Choose the code model from:
104
105                 default: Target default code model
106                 tiny: Tiny code model
107                 small: Small code model
108                 kernel: Kernel code model
109                 medium: Medium code model
110                 large: Large code model
111
112       -disable-post-RA-scheduler
113              Disable scheduling after register allocation.
114
115       -disable-spill-fusing
116              Disable fusing of spill code into instructions.
117
118       -jit-enable-eh
119              Exception  handling  should  be enabled in the just-in-time com‐
120              piler.
121
122       -join-liveintervals
123              Coalesce copies (default=true).
124
125       -nozero-initialized-in-bss
126              Don't place zero-initialized symbols into the BSS section.
127
128       -pre-RA-sched=scheduler
129              Instruction schedulers available (before register allocation):
130
131                 =default: Best scheduler for the target
132                 =none: No scheduling: breadth first sequencing
133                 =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
134                 =simple-noitin: Simple two pass scheduling: Same as simple except using generic latency
135                 =list-burr: Bottom-up register reduction list scheduling
136                 =list-tdrr: Top-down register reduction list scheduling
137                 =list-td: Top-down list scheduler -print-machineinstrs - Print generated machine code
138
139       -regalloc=allocator
140              Register allocator to use (default=linearscan)
141
142                 =bigblock: Big-block register allocator
143                 =linearscan: linear scan register allocator =local -   local register allocator
144                 =simple: simple register allocator
145
146       -relocation-model=model
147              Choose relocation model from:
148
149                 =default: Target default relocation model
150                 =static: Non-relocatable code =pic -   Fully relocatable, position independent code
151                 =dynamic-no-pic: Relocatable external references, non-relocatable code
152
153       -spiller
154              Spiller to use (default=local)
155
156                 =simple: simple spiller
157                 =local: local spiller
158
159       -x86-asm-syntax=syntax
160              Choose style of code to emit from X86 backend:
161
162                 =att: Emit AT&T-style assembly
163                 =intel: Emit Intel-style assembly
164

EXIT STATUS

166       If lli fails to load the program, it will exit with an exit code of  1.
167       Otherwise, it will return the exit code of the program it executes.
168

SEE ALSO

170       llc(1)
171

AUTHOR

173       Maintained by the LLVM Team (https://llvm.org/).
174
176       2003-2021, LLVM Project
177
178
179
180
18111                                2021-07-22                            LLI(1)
Impressum