1DPGEN_RF1D(3)           Alliance - genlib User's Manual          DPGEN_RF1D(3)
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NAME

6       DPGEN_RF1D, DPGEN_RF1DR0 - Register File with Decoder Macro-Generator
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SYNOPSIS

9       #include  <genlib.h>
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11       void GENLIB_MACRO (DPGEN_RF1D, char *modelname, long flags, long N);
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13       void GENLIB_MACRO (DPGEN_RF1DR0, char *modelname, long flags, long N);
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DESCRIPTION

16       Generate  a  register  file  of  regNumber words of N bits with decoder
17       named modelname. The DPGEN_RF1DR0 variant differs from  the  DPGEN_RF1D
18       in  that  the  register of address zero is stuck to zero. You can write
19       into it, it will not change the value. When read, it will always return
20       zero.
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22       How it works :
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24       · datain0 and datain1 : the two write busses. Only one is used to actu‐
25         ally write the register word, it is selected by the sel signal.
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27       · sel : when set to '0' the datain0 is used to write the register word,
28         otherwise it will be datain1.
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30       · adr,  adw : the width (Y) of those signals is computed from regNumber
31         : Y = log2(regNumber).
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33       · wen and ren : write enable and read enable, allows reading and  writ‐
34         ing when sets to '1'.
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36   TERMINAL NAMES
37       1. ck : clock signal (input, 1 bit).
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39       2. sel : select the write bus (input, 1 bit).
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41       3. wen : write enable (input, 1 bit).
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43       4. ren : read enable (input, 1 bit).
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45       5. adr : the read address (input, Y bits).
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47       6. adw : the write address (input, Y bits).
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49       7. datain0 :  first write bus (input, N bits).
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51       8. datain1 :  second write bus (input, N bits).
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53       9. dataout : read bus (output, N bits).
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55       10.
56          vdd : power.
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58       11.
59          vss : ground.
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EXAMPLE

62       GENLIB_MACRO(DPGEN_RF1D, "model_rf1dx8_32"
63                              , F_BEHAV|F_PLACE
64                              , 32  /* Words size.      */
65                              , 8   /* Number of words. */
66                              );
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68       GENLIB_LOINS( "model_rf1dx8_32"
69                   , "instance1_rf1d_32"
70                   , "ck"
71                   , "sel"
72                   , "wen"
73                   , "ren"
74                   , "adr[2:0]"
75                   , "adw[2:0]"
76                   , "datain0[31:0]"
77                   , "datain1[31:0]"
78                   , "dataout[31:0]"
79                   , "vdd", "vss", NULL
80                   );
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SEE ALSO

84       GENLIB_MACRO(3), genlib(1)
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88ASIM/LIP6                        30 July 2004                    DPGEN_RF1D(3)
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