1DLYS(5)                       File Formats Manual                      DLYS(5)
2
3
4

NAME

6       dlys  -  format  of  .dlys files read by the SCALD simulator and timing
7       verifier
8
9

DESCRIPTION

11       The SCALD simulator and timing verifier can  accept  information  about
12       the  actual  delays  of  wires in a circuit.  This delay information is
13       described in a .dlys file, which consists of a sequence of records, one
14       for  each  electrical net.  Each record begins with the signal name for
15       the net (note that this is the SCALD signal name, i.e., the name  given
16       by  the  user to the entire net, and not usually the name of one of the
17       pins in the net), followed by an =, then a comma-separated list of  the
18       terminals  in  the net and their associated delay, with the list termi‐
19       nated by a semicolon.  The end of the file  is  marked  with  a  second
20       semicolon.
21
22       The elements of the comma-separated list for each net take the form
23
24               location [min:max]
25
26       where  location is the full hierarchical SCALD name of the physical pin
27       to which the delay is computed, and min and max are the  best-case  and
28       worst-case wire delay in nanoseconds (both are floating-point numbers).
29       The assumption is that only a single driver  exists  per  net,  so  all
30       delays  are  computed from this driver.  If a net has multiple drivers,
31       then the interpretation of delays is up to  the  program  reading  this
32       file  (e.g,  min delays are taken from the fastest driver, max from the
33       slowest).
34
35       Here is an example .dlys file:
36
37       (APS )ALU STATUS BITS I1<0> =
38          (APS MR 3V6 R1 1P )IN#63[ 0.3 : 0.4 ],
39          (APS APS 4RI RFC RF )OUT[ 0.5 : 0.7 ];
40       (APS )ALU STATUS BITS I1<1> =
41          (APS APS 4ALUD DCD )AN#12[ 1.4 : 1.6 ],
42          (APS APS 4ALUD DCD )AN#8[ 1.1 : 1.3 ],
43          (APS APS 4ALUD DCD )AN#9[ 1.1 : 1.3 ],
44          (APS APS 4ALUD DCD )AN#10[ 1.1 : 1.3 ],
45          (APS APS 4ALUD DCD )AN#11[ 1.1 : 1.3 ],
46          (APS MR 3V2 R1 1P )#23[ 0.6 : 0.8 ],
47          (APS MR 3V6 R1 1P )#62[ 0.3 : 0.4 ],
48          (APS APS 4ALUD DCD )[ 0.4 : 0.6 ],
49          (APS APS 4ALUD DCD )#1[ 0.4 : 0.6 ],
50          (APS APS 4ALUD DCD )#2[ 0.4 : 0.6 ],
51          (APS APS 4ALUD DCD )#3[ 0.4 : 0.6 ],
52          (APS APS 4ALUD DCD )#4[ 0.7 : 0.8 ],
53          (APS APS 4ALUD DCD )#5[ 0.7 : 0.8 ];
54       ;
55
56       Although it is not good practice, it is possible to omit the actual pin
57       names  from  the location names and only give the path to the part; the
58       example above shows several cases where the final pin name is  missing.
59       Since the timing verifier and simulator have the original SCALD netlist
60       available, they are usually able to use the signal  name  to  determine
61       the  net, and then use the part's path to identify which pin of the net
62       is meant.  This is accurate when a net connects to at most one pin  per
63       part;  if it connects to more than one pin per part then there is ambi‐
64       guity over which pin is meant.  Usually, though, this ambiguity results
65       in  only  a  small inaccuracy, since the delay to different pins on the
66       same part is usually similar.  Also, if delay is capacitive, the  delay
67       to  all  pins  in a net will be the same anyway, so there is no inaccu‐
68       racy.
69
70

SEE ALSO

72       ext2dlys(1), ext(5), sim(5)
73
74

BUGS

76       There should be some way to specify which pins are  drivers  and  which
77       are receivers in a net.
78
79       The  ability  to omit pin names is dangerous; although it usually works
80       it can introduce large inaccuracies when the parts are  large  compared
81       to the sizes of the wires used to connect them, as might be the case on
82       a silicon PCB.
83
84
85
86                                                                       DLYS(5)
Impressum