1QEMU-CPU-MODELS(7) QEMU QEMU-CPU-MODELS(7)
2
6 qemu-cpu-models - QEMU CPU Models
7
9 QEMU CPU Modelling Infrastructure manual
10
12 Recommendations for KVM CPU model configuration on x86 hosts
13 The information that follows provides recommendations for configuring
14 CPU models on x86 hosts. The goals are to maximise performance, while
15 protecting guest OS against various CPU hardware flaws, and optionally
16 enabling live migration between hosts with heterogeneous CPU models.
17 Two ways to configure CPU models with QEMU / KVM
19 1. Host passthrough
20 This passes the host CPU model features, model, stepping, exactly to
22 the guest. Note that KVM may filter out some host CPU model features
23 if they cannot be supported with virtualization. Live migration is
24 unsafe when this mode is used as libvirt / QEMU cannot guarantee a
25 stable CPU is exposed to the guest across hosts. This is the recom‐
26 mended CPU to use, provided live migration is not required.
27 2. Named model
29 QEMU comes with a number of predefined named CPU models, that typi‐
31 cally refer to specific generations of hardware released by Intel
32 and AMD. These allow the guest VMs to have a degree of isolation
33 from the host CPU, allowing greater flexibility in live migrating
34 between hosts with differing hardware. @end table
35 In both cases, it is possible to optionally add or remove individual
37 CPU features, to alter what is presented to the guest by default.
38 Libvirt supports a third way to configure CPU models known as "Host
40 model". This uses the QEMU "Named model" feature, automatically pick‐
41 ing a CPU model that is similar the host CPU, and then adding extra
42 features to approximate the host model as closely as possible. This
43 does not guarantee the CPU family, stepping, etc will precisely match
44 the host CPU, as they would with "Host passthrough", but gives much of
45 the benefit of passthrough, while making live migration safe.
46 ABI compatibility levels for CPU models
48 The x86_64 architecture has a number of ABI compatibility levels de‐
49 fined. Traditionally most operating systems and toolchains would only
50 target the original baseline ABI. It is expected that in future OS and
51 toolchains are likely to target newer ABIs. The table that follows il‐
52 lustrates which ABI compatibility levels can be satisfied by the QEMU
53 CPU models. Note that the table only lists the long term stable CPU
54 model versions (eg Haswell-v4). In addition to what is listed, there
55 are also many CPU model aliases which resolve to a different CPU model
56 version, depending on the machine type is in use.
57 x86-64 ABI compatibility levels
59 ┌───────────────┬──────────┬────┬────┬────┐
60 │Model │ baseline │ v2 │ v3 │ v4 │
61 ├───────────────┼──────────┼────┼────┼────┤
62 │486-v1 │ │ │ │ │
63 ├───────────────┼──────────┼────┼────┼────┤
64 │Broadwell-v1 │ ✅ │ ✅ │ ✅ │ │
65 └───────────────┴──────────┴────┴────┴────┘
66 │Broadwell-v2 │ ✅ │ ✅ │ ✅ │ │
68 ├───────────────┼──────────┼────┼────┼────┤
69 │Broadwell-v3 │ ✅ │ ✅ │ ✅ │ │
70 ├───────────────┼──────────┼────┼────┼────┤
71 │Broadwell-v4 │ ✅ │ ✅ │ ✅ │ │
72 ├───────────────┼──────────┼────┼────┼────┤
73 │Cascade‐ │ ✅ │ ✅ │ ✅ │ ✅ │
74 │lake-Server-v1 │ │ │ │ │
75 ├───────────────┼──────────┼────┼────┼────┤
76 │Cascade‐ │ ✅ │ ✅ │ ✅ │ ✅ │
77 │lake-Server-v2 │ │ │ │ │
78 ├───────────────┼──────────┼────┼────┼────┤
79 │Cascade‐ │ ✅ │ ✅ │ ✅ │ ✅ │
80 │lake-Server-v3 │ │ │ │ │
81 ├───────────────┼──────────┼────┼────┼────┤
82 │Cascade‐ │ ✅ │ ✅ │ ✅ │ ✅ │
83 │lake-Server-v4 │ │ │ │ │
84 ├───────────────┼──────────┼────┼────┼────┤
85 │Conroe-v1 │ ✅ │ │ │ │
86 ├───────────────┼──────────┼────┼────┼────┤
87 │Cooperlake-v1 │ ✅ │ ✅ │ ✅ │ ✅ │
88 ├───────────────┼──────────┼────┼────┼────┤
89 │Denverton-v1 │ ✅ │ ✅ │ │ │
90 ├───────────────┼──────────┼────┼────┼────┤
91 │Denverton-v2 │ ✅ │ ✅ │ │ │
92 ├───────────────┼──────────┼────┼────┼────┤
93 │Dhyana-v1 │ ✅ │ ✅ │ ✅ │ │
94 ├───────────────┼──────────┼────┼────┼────┤
95 │EPYC-Milan-v1 │ ✅ │ ✅ │ ✅ │ │
96 ├───────────────┼──────────┼────┼────┼────┤
97 │EPYC-Rome-v1 │ ✅ │ ✅ │ ✅ │ │
98 ├───────────────┼──────────┼────┼────┼────┤
99 │EPYC-Rome-v2 │ ✅ │ ✅ │ ✅ │ │
100 ├───────────────┼──────────┼────┼────┼────┤
101 │EPYC-v1 │ ✅ │ ✅ │ ✅ │ │
102 ├───────────────┼──────────┼────┼────┼────┤
103 │EPYC-v2 │ ✅ │ ✅ │ ✅ │ │
104 ├───────────────┼──────────┼────┼────┼────┤
105 │EPYC-v3 │ ✅ │ ✅ │ ✅ │ │
106 ├───────────────┼──────────┼────┼────┼────┤
107 │Haswell-v1 │ ✅ │ ✅ │ ✅ │ │
108 ├───────────────┼──────────┼────┼────┼────┤
109 │Haswell-v2 │ ✅ │ ✅ │ ✅ │ │
110 ├───────────────┼──────────┼────┼────┼────┤
111 │Haswell-v3 │ ✅ │ ✅ │ ✅ │ │
112 ├───────────────┼──────────┼────┼────┼────┤
113 │Haswell-v4 │ ✅ │ ✅ │ ✅ │ │
114 ├───────────────┼──────────┼────┼────┼────┤
115 │Ice‐ │ ✅ │ ✅ │ ✅ │ │
116 │lake-Client-v1 │ │ │ │ │
117 ├───────────────┼──────────┼────┼────┼────┤
118 │Ice‐ │ ✅ │ ✅ │ ✅ │ │
119 │lake-Client-v2 │ │ │ │ │
120 ├───────────────┼──────────┼────┼────┼────┤
121 │Ice‐ │ ✅ │ ✅ │ ✅ │ ✅ │
122 │lake-Server-v1 │ │ │ │ │
123 ├───────────────┼──────────┼────┼────┼────┤
124 │Ice‐ │ ✅ │ ✅ │ ✅ │ ✅ │
125 │lake-Server-v2 │ │ │ │ │
126 ├───────────────┼──────────┼────┼────┼────┤
127 │Ice‐ │ ✅ │ ✅ │ ✅ │ ✅ │
128 │lake-Server-v3 │ │ │ │ │
129 └───────────────┴──────────┴────┴────┴────┘
130 │Ice‐ │ ✅ │ ✅ │ ✅ │ ✅ │
134 │lake-Server-v4 │ │ │ │ │
135 ├───────────────┼──────────┼────┼────┼────┤
136 │IvyBridge-v1 │ ✅ │ ✅ │ │ │
137 ├───────────────┼──────────┼────┼────┼────┤
138 │IvyBridge-v2 │ ✅ │ ✅ │ │ │
139 ├───────────────┼──────────┼────┼────┼────┤
140 │KnightsMill-v1 │ ✅ │ ✅ │ ✅ │ │
141 ├───────────────┼──────────┼────┼────┼────┤
142 │Nehalem-v1 │ ✅ │ ✅ │ │ │
143 ├───────────────┼──────────┼────┼────┼────┤
144 │Nehalem-v2 │ ✅ │ ✅ │ │ │
145 ├───────────────┼──────────┼────┼────┼────┤
146 │Opteron_G1-v1 │ ✅ │ │ │ │
147 ├───────────────┼──────────┼────┼────┼────┤
148 │Opteron_G2-v1 │ ✅ │ │ │ │
149 ├───────────────┼──────────┼────┼────┼────┤
150 │Opteron_G3-v1 │ ✅ │ │ │ │
151 ├───────────────┼──────────┼────┼────┼────┤
152 │Opteron_G4-v1 │ ✅ │ ✅ │ │ │
153 ├───────────────┼──────────┼────┼────┼────┤
154 │Opteron_G5-v1 │ ✅ │ ✅ │ │ │
155 ├───────────────┼──────────┼────┼────┼────┤
156 │Penryn-v1 │ ✅ │ │ │ │
157 ├───────────────┼──────────┼────┼────┼────┤
158 │SandyBridge-v1 │ ✅ │ ✅ │ │ │
159 ├───────────────┼──────────┼────┼────┼────┤
160 │SandyBridge-v2 │ ✅ │ ✅ │ │ │
161 ├───────────────┼──────────┼────┼────┼────┤
162 │Sky‐ │ ✅ │ ✅ │ ✅ │ │
163 │lake-Client-v1 │ │ │ │ │
164 ├───────────────┼──────────┼────┼────┼────┤
165 │Sky‐ │ ✅ │ ✅ │ ✅ │ │
166 │lake-Client-v2 │ │ │ │ │
167 ├───────────────┼──────────┼────┼────┼────┤
168 │Sky‐ │ ✅ │ ✅ │ ✅ │ │
169 │lake-Client-v3 │ │ │ │ │
170 ├───────────────┼──────────┼────┼────┼────┤
171 │Sky‐ │ ✅ │ ✅ │ ✅ │ ✅ │
172 │lake-Server-v1 │ │ │ │ │
173 ├───────────────┼──────────┼────┼────┼────┤
174 │Sky‐ │ ✅ │ ✅ │ ✅ │ ✅ │
175 │lake-Server-v2 │ │ │ │ │
176 ├───────────────┼──────────┼────┼────┼────┤
177 │Sky‐ │ ✅ │ ✅ │ ✅ │ ✅ │
178 │lake-Server-v3 │ │ │ │ │
179 ├───────────────┼──────────┼────┼────┼────┤
180 │Sky‐ │ ✅ │ ✅ │ ✅ │ ✅ │
181 │lake-Server-v4 │ │ │ │ │
182 ├───────────────┼──────────┼────┼────┼────┤
183 │Snowridge-v1 │ ✅ │ ✅ │ │ │
184 ├───────────────┼──────────┼────┼────┼────┤
185 │Snowridge-v2 │ ✅ │ ✅ │ │ │
186 ├───────────────┼──────────┼────┼────┼────┤
187 │Westmere-v1 │ ✅ │ ✅ │ │ │
188 ├───────────────┼──────────┼────┼────┼────┤
189 │Westmere-v2 │ ✅ │ ✅ │ │ │
190 ├───────────────┼──────────┼────┼────┼────┤
191 │athlon-v1 │ │ │ │ │
192 ├───────────────┼──────────┼────┼────┼────┤
193 │core2duo-v1 │ ✅ │ │ │ │
194 ├───────────────┼──────────┼────┼────┼────┤
195 │coreduo-v1 │ │ │ │ │
196 └───────────────┴──────────┴────┴────┴────┘
197 │kvm32-v1 │ │ │ │ │
200 ├───────────────┼──────────┼────┼────┼────┤
201 │kvm64-v1 │ ✅ │ │ │ │
202 ├───────────────┼──────────┼────┼────┼────┤
203 │n270-v1 │ │ │ │ │
204 ├───────────────┼──────────┼────┼────┼────┤
205 │pentium-v1 │ │ │ │ │
206 ├───────────────┼──────────┼────┼────┼────┤
207 │pentium2-v1 │ │ │ │ │
208 ├───────────────┼──────────┼────┼────┼────┤
209 │pentium3-v1 │ │ │ │ │
210 ├───────────────┼──────────┼────┼────┼────┤
211 │phenom-v1 │ ✅ │ │ │ │
212 ├───────────────┼──────────┼────┼────┼────┤
213 │qemu32-v1 │ │ │ │ │
214 ├───────────────┼──────────┼────┼────┼────┤
215 │qemu64-v1 │ ✅ │ │ │ │
216 └───────────────┴──────────┴────┴────┴────┘
217 Preferred CPU models for Intel x86 hosts
219 The following CPU models are preferred for use on Intel hosts. Admin‐
220 istrators / applications are recommended to use the CPU model that
221 matches the generation of the host CPUs in use. In a deployment with a
222 mixture of host CPU models between machines, if live migration compati‐
223 bility is required, use the newest CPU model that is compatible across
224 all desired hosts.
225 Cascadelake-Server, Cascadelake-Server-noTSX
227 Intel Xeon Processor (Cascade Lake, 2019), with "stepping" lev‐
228 els 6 or 7 only. (The Cascade Lake Xeon processor with stepping
229 5 is vulnerable to MDS variants.)
230 Skylake-Server, Skylake-Server-IBRS, Skylake-Server-IBRS-noTSX
232 Intel Xeon Processor (Skylake, 2016)
233 Skylake-Client, Skylake-Client-IBRS, Skylake-Client-noTSX-IBRS}
235 Intel Core Processor (Skylake, 2015)
236 Broadwell, Broadwell-IBRS, Broadwell-noTSX, Broadwell-noTSX-IBRS
238 Intel Core Processor (Broadwell, 2014)
239 Haswell, Haswell-IBRS, Haswell-noTSX, Haswell-noTSX-IBRS
241 Intel Core Processor (Haswell, 2013)
242 IvyBridge, IvyBridge-IBR
244 Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)
245 SandyBridge, SandyBridge-IBRS
247 Intel Xeon E312xx (Sandy Bridge, 2011)
248 Westmere, Westmere-IBRS
250 Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)
251 Nehalem, Nehalem-IBRS
253 Intel Core i7 9xx (Nehalem Class Core i7, 2008)
254 Penryn Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)
256 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)
258 Important CPU features for Intel x86 hosts
260 The following are important CPU features that should be used on Intel
261 x86 hosts, when available in the host CPU. Some of them require ex‐
262 plicit configuration to enable, as they are not included by default in
263 some, or all, of the named CPU models listed above. In general all of
264 these features are included if using "Host passthrough" or "Host
265 model".
266 pcid Recommended to mitigate the cost of the Meltdown (CVE-2017-5754)
268 fix.
269 Included by default in Haswell, Broadwell & Skylake Intel CPU
271 models.
272 Should be explicitly turned on for Westmere, SandyBridge, and
274 IvyBridge Intel CPU models. Note that some desktop/mobile West‐
275 mere CPUs cannot support this feature.
276 spec-ctrl
278 Required to enable the Spectre v2 (CVE-2017-5715) fix.
279 Included by default in Intel CPU models with -IBRS suffix.
281 Must be explicitly turned on for Intel CPU models without -IBRS
283 suffix.
284 Requires the host CPU microcode to support this feature before
286 it can be used for guest CPUs.
287 stibp Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in
289 some operating systems.
290 Must be explicitly turned on for all Intel CPU models.
292 Requires the host CPU microcode to support this feature before
294 it can be used for guest CPUs.
295 ssbd Required to enable the CVE-2018-3639 fix.
297 Not included by default in any Intel CPU model.
299 Must be explicitly turned on for all Intel CPU models.
301 Requires the host CPU microcode to support this feature before
303 it can be used for guest CPUs.
304 pdpe1gb
306 Recommended to allow guest OS to use 1GB size pages.
307 Not included by default in any Intel CPU model.
309 Should be explicitly turned on for all Intel CPU models.
311 Note that not all CPU hardware will support this feature.
313 md-clear
315 Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127,
316 CVE-2018-12130, CVE-2019-11091) fixes.
317 Not included by default in any Intel CPU model.
319 Must be explicitly turned on for all Intel CPU models.
321 Requires the host CPU microcode to support this feature before
323 it can be used for guest CPUs.
324 mds-no Recommended to inform the guest OS that the host is not vulnera‐
326 ble to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS]
327 CVE-2018-12127, [MSBDS] CVE-2018-12126).
328 This is an MSR (Model-Specific Register) feature rather than a
330 CPUID feature, so it will not appear in the Linux /proc/cpuinfo
331 in the host or guest. Instead, the host kernel uses it to popu‐
332 late the MDS vulnerability file in sysfs.
333 So it should only be enabled for VMs if the host reports
335 @code{Not affected} in the /sys/devices/system/cpu/vulnerabili‐
336 ties/mds file.
337 taa-no Recommended to inform that the guest that the host is not vul‐
339 nerable to CVE-2019-11135, TSX Asynchronous Abort (TAA).
340 This too is an MSR feature, so it does not show up in the Linux
342 /proc/cpuinfo in the host or guest.
343 It should only be enabled for VMs if the host reports Not af‐
345 fected in the /sys/devices/system/cpu/vulnerabili‐
346 ties/tsx_async_abort file.
347 tsx-ctrl
349 Recommended to inform the guest that it can disable the Intel
350 TSX (Transactional Synchronization Extensions) feature; or, if
351 the processor is vulnerable, use the Intel VERW instruction (a
352 processor-level instruction that performs checks on memory ac‐
353 cess) as a mitigation for the TAA vulnerability. (For details,
354 refer to Intel's deep dive into MDS.)
355 Expose this to the guest OS if and only if: (a) the host has TSX
357 enabled; and (b) the guest has rtm CPU flag enabled.
358 By disabling TSX, KVM-based guests can avoid paying the price of
360 mitigating TSX-based attacks.
361 Note that tsx-ctrl too is an MSR feature, so it does not show up
363 in the Linux /proc/cpuinfo in the host or guest.
364 To validate that Intel TSX is indeed disabled for the guest,
366 there are two ways: (a) check for the absence of rtm in the
367 guest's /proc/cpuinfo; or (b) the /sys/devices/system/cpu/vul‐
368 nerabilities/tsx_async_abort file in the guest should report
369 Mitigation: TSX disabled.
370 Preferred CPU models for AMD x86 hosts
372 The following CPU models are preferred for use on AMD hosts. Adminis‐
373 trators / applications are recommended to use the CPU model that
374 matches the generation of the host CPUs in use. In a deployment with a
375 mixture of host CPU models between machines, if live migration compati‐
376 bility is required, use the newest CPU model that is compatible across
377 all desired hosts.
378 EPYC, EPYC-IBPB
380 AMD EPYC Processor (2017)
381 Opteron_G5
383 AMD Opteron 63xx class CPU (2012)
384 Opteron_G4
386 AMD Opteron 62xx class CPU (2011)
387 Opteron_G3
389 AMD Opteron 23xx (Gen 3 Class Opteron, 2009)
390 Opteron_G2
392 AMD Opteron 22xx (Gen 2 Class Opteron, 2006)
393 Opteron_G1
395 AMD Opteron 240 (Gen 1 Class Opteron, 2004)
396 Important CPU features for AMD x86 hosts
398 The following are important CPU features that should be used on AMD x86
399 hosts, when available in the host CPU. Some of them require explicit
400 configuration to enable, as they are not included by default in some,
401 or all, of the named CPU models listed above. In general all of these
402 features are included if using "Host passthrough" or "Host model".
403 ibpb Required to enable the Spectre v2 (CVE-2017-5715) fix.
405 Included by default in AMD CPU models with -IBPB suffix.
407 Must be explicitly turned on for AMD CPU models without -IBPB
409 suffix.
410 Requires the host CPU microcode to support this feature before
412 it can be used for guest CPUs.
413 stibp Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in
415 some operating systems.
416 Must be explicitly turned on for all AMD CPU models.
418 Requires the host CPU microcode to support this feature before
420 it can be used for guest CPUs.
421 virt-ssbd
423 Required to enable the CVE-2018-3639 fix
424 Not included by default in any AMD CPU model.
426 Must be explicitly turned on for all AMD CPU models.
428 This should be provided to guests, even if amd-ssbd is also pro‐
430 vided, for maximum guest compatibility.
431 Note for some QEMU / libvirt versions, this must be force en‐
433 abled when when using "Host model", because this is a virtual
434 feature that doesn't exist in the physical host CPUs.
435 amd-ssbd
437 Required to enable the CVE-2018-3639 fix
438 Not included by default in any AMD CPU model.
440 Must be explicitly turned on for all AMD CPU models.
442 This provides higher performance than virt-ssbd so should be ex‐
444 posed to guests whenever available in the host. virt-ssbd should
445 none the less also be exposed for maximum guest compatibility as
446 some kernels only know about virt-ssbd.
447 amd-no-ssb
449 Recommended to indicate the host is not vulnerable CVE-2018-3639
450 Not included by default in any AMD CPU model.
452 Future hardware generations of CPU will not be vulnerable to
454 CVE-2018-3639, and thus the guest should be told not to enable
455 its mitigations, by exposing amd-no-ssb. This is mutually exclu‐
456 sive with virt-ssbd and amd-ssbd.
457 pdpe1gb
459 Recommended to allow guest OS to use 1GB size pages
460 Not included by default in any AMD CPU model.
462 Should be explicitly turned on for all AMD CPU models.
464 Note that not all CPU hardware will support this feature.
466 Default x86 CPU models
468 The default QEMU CPU models are designed such that they can run on all
469 hosts. If an application does not wish to do perform any host compati‐
470 bility checks before launching guests, the default is guaranteed to
471 work.
472 The default CPU models will, however, leave the guest OS vulnerable to
474 various CPU hardware flaws, so their use is strongly discouraged. Ap‐
475 plications should follow the earlier guidance to setup a better CPU
476 configuration, with host passthrough recommended if live migration is
477 not needed.
478 qemu32, qemu64
480 QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)
481 qemu64 is used for x86_64 guests and qemu32 is used for i686 guests,
483 when no -cpu argument is given to QEMU, or no <cpu> is provided in lib‐
484 virt XML.
485 Other non-recommended x86 CPUs
487 The following CPUs models are compatible with most AMD and Intel x86
488 hosts, but their usage is discouraged, as they expose a very limited
489 featureset, which prevents guests having optimal performance.
490 kvm32, kvm64
492 Common KVM processor (32 & 64 bit variants).
493 Legacy models just for historical compatibility with ancient
495 QEMU versions.
496 486, athlon, phenom, coreduo, core2duo, n270, pentium, pentium2, pen‐
498 tium3
499 Various very old x86 CPU models, mostly predating the introduc‐
500 tion of hardware assisted virtualization, that should thus not
501 be required for running virtual machines.
502 Syntax for configuring CPU models
504 The examples below illustrate the approach to configuring the various
505 CPU models / features in QEMU and libvirt.
506 QEMU command line
508 Host passthrough:
509 qemu-system-x86_64 -cpu host
511 Host passthrough with feature customization:
513 qemu-system-x86_64 -cpu host,vmx=off,...
515 Named CPU models:
517 qemu-system-x86_64 -cpu Westmere
519 Named CPU models with feature customization:
521 qemu-system-x86_64 -cpu Westmere,pcid=on,...
523 Libvirt guest XML
525 Host passthrough:
526 <cpu mode='host-passthrough'/>
528 Host passthrough with feature customization:
530 <cpu mode='host-passthrough'>
532 <feature name="vmx" policy="disable"/>
533 ...
534 </cpu>
535 Host model:
537 <cpu mode='host-model'/>
539 Host model with feature customization:
541 <cpu mode='host-model'>
543 <feature name="vmx" policy="disable"/>
544 ...
545 </cpu>
546 Named model:
548 <cpu mode='custom'>
550 <model name="Westmere"/>
551 </cpu>
552 Named model with feature customization:
554 <cpu mode='custom'>
556 <model name="Westmere"/>
557 <feature name="pcid" policy="require"/>
558 ...
559 </cpu>
560 Supported CPU model configurations on MIPS hosts
562 QEMU supports variety of MIPS CPU models:
563 Supported CPU models for MIPS32 hosts
565 The following CPU models are supported for use on MIPS32 hosts. Admin‐
566 istrators / applications are recommended to use the CPU model that
567 matches the generation of the host CPUs in use. In a deployment with a
568 mixture of host CPU models between machines, if live migration compati‐
569 bility is required, use the newest CPU model that is compatible across
570 all desired hosts.
571 mips32r6-generic
573 MIPS32 Processor (Release 6, 2015)
574 P5600 MIPS32 Processor (P5600, 2014)
576 M14K, M14Kc
578 MIPS32 Processor (M14K, 2009)
579 74Kf MIPS32 Processor (74K, 2007)
581 34Kf MIPS32 Processor (34K, 2006)
583 24Kc, 24KEc, 24Kf
585 MIPS32 Processor (24K, 2003)
586 4Kc, 4Km, 4KEcR1, 4KEmR1, 4KEc, 4KEm
588 MIPS32 Processor (4K, 1999)
589 Supported CPU models for MIPS64 hosts
591 The following CPU models are supported for use on MIPS64 hosts. Admin‐
592 istrators / applications are recommended to use the CPU model that
593 matches the generation of the host CPUs in use. In a deployment with a
594 mixture of host CPU models between machines, if live migration compati‐
595 bility is required, use the newest CPU model that is compatible across
596 all desired hosts.
597 I6400 MIPS64 Processor (Release 6, 2014)
599 Loongson-2E
601 MIPS64 Processor (Loongson 2, 2006)
602 Loongson-2F
604 MIPS64 Processor (Loongson 2, 2008)
605 Loongson-3A1000
607 MIPS64 Processor (Loongson 3, 2010)
608 Loongson-3A4000
610 MIPS64 Processor (Loongson 3, 2018)
611 mips64dspr2
613 MIPS64 Processor (Release 2, 2006)
614 MIPS64R2-generic, 5KEc, 5KEf
616 MIPS64 Processor (Release 2, 2002)
617 20Kc MIPS64 Processor (20K, 2000
619 5Kc, 5Kf
621 MIPS64 Processor (5K, 1999)
622 VR5432 MIPS64 Processor (VR, 1998)
624 R4000 MIPS64 Processor (MIPS III, 1991)
626 Supported CPU models for nanoMIPS hosts
628 The following CPU models are supported for use on nanoMIPS hosts. Ad‐
629 ministrators / applications are recommended to use the CPU model that
630 matches the generation of the host CPUs in use. In a deployment with a
631 mixture of host CPU models between machines, if live migration compati‐
632 bility is required, use the newest CPU model that is compatible across
633 all desired hosts.
634 I7200 MIPS I7200 (nanoMIPS, 2018)
636 Preferred CPU models for MIPS hosts
638 The following CPU models are preferred for use on different MIPS hosts:
639 MIPS III
641 R4000
642 MIPS32R2
644 34Kf
645 MIPS64R6
647 I6400
648 nanoMIPS
650 I7200
651
653 The HTML documentation of QEMU for more precise information and Linux
654 user mode emulator invocation.
655
657 The QEMU Project developers
658
660 2023, The QEMU Project Developers
6617.0.0 Jan 19, 2023 QEMU-CPU-MODELS(7)