boog(1alc)

1BOOG(1)                    CAO-VLSI Reference Manual                   BOOG(1)
2
3
4

NAME

6       BooG - Binding and Optimizing On Gates.
7
8
9
10

ORIGIN

12       This software belongs to the  ALLIANCE CAD SYSTEM developed by the ASIM
13       team at LIP6 laboratory of Université Pierre et Marie CURIE, in  Paris,
14       France.
15
16       Web : http://asim.lip6.fr/recherche/alliance/
17       E-mail : alliance-users@asim.lip6.fr
18
19

SYNOPSIS

21       boog  [-hmxold] input_file output_file  [lax_file]
22
23

DESCRIPTION

25       boog  is  a mapper of a behavioural description onto a predefined stan‐
26       dard cell library as SXLIB.  It is the second step of the logic synthe‐
27       sis: it builds a gate network using a standard cell library.
28
29         Input file description
30       The  logic level behavioural description (.vbe file) uses the same VHDL
31       subset as the logic simulator asimut,  the  FSM  synthesizer  syf,  the
32       functional  abstractor  yagle  and the formal prover proof (for further
33       information about the subset of VHDL, see the "vbe" manual).
34       Some constraints due to hardware mapping exist.  These  attributes  are
35       only  supported  by  technology mapping onto a standard cell library as
36       sxlib.
37       For the register signal description, only one condition statement  must
38       appear. STABLE must be strictely used as a negativ motion and joined to
39       clock setup value. Setup can be on high or low value, but it  would  be
40       worthy to choose it accordingly with hardware register cell.
41       # Example
42               label: BLOCK (NOT ck 'STABLE and ck='1')
43               BEGIN
44                   reg <= GUARDED expr;
45               END BLOCK;
46
47       You can also put a write enable condition to your register:
48               label: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
49               BEGIN
50                   reg <= GUARDED expr;
51               END BLOCK;
52
53       A  special  feature  has been introduced in the VHDL subset in order to
54       allow the don't care description for external outputs and internal reg‐
55       isters  :  A  bit  signal can take the 'd' value.  This value is inter‐
56       preted as a '0' by the logic simulator asimut.  Don't Cares  are  auto‐
57       matically generated by syf in the resulting '.vbe' file.
58
59
60         Output file description
61       A  pure  standard cell netlist is produced by boog. This file is desti‐
62       nated for /fBloon/fP  alliance  utility  to  improve  RC  delays.   Any
63       equipotential  keeps  its  name from connector to connector. In trouble
64       case, buffers are inserted to respect this VHDL constraint.
65
66         lax Parameter file description
67       The lax file is common with other logic synthesis tools and is used for
68       driving the synthesis process.  See lax[24m(5) manual for more detail.
69
70       lax  uses  a  lot  of  parameters  to guide every step of the synthesis
71       process.  Some parameters are globally used (for example,  optimization
72       level  whereas  others  are specifically used (load capacitance for the
73       netlist optimization only).  Here is the  default  lax  file  (see  the
74       user's  manual  for  further information about the syntax of the '.lax'
75       file):
76
77          Optimization mode = 2 (50% area - 50% delay)
78          Input impedance = 0
79          Output capacitance = 0
80          Delayed input = none
81          Auxiliary signal saved = none
82
83
84         Mapping with a standard cell library
85       Every cell appearing in the directory defined by the environment  vari‐
86       able  MBK_TARGET_LIB  may be used by boog since they are described as a
87       '.vbe' file. There are some restrictions about the  type  of  the  cell
88       used. Every cell has to have only one output.  The cell must be charac‐
89       terized. The timing and area information required by boog are specified
90       in the "generic" clause of the ".vbe" file.
91
92

OPTION

94       -h        Help mode. Displays possible uses of boog.
95
96       -m optim_mode
97                 Optimization  mode.  Can  be defined in lax file, it's only a
98                 shortcut to define it on command line. This mode  number  has
99                 an  array  defined  between  0 and 4. It indicates the way of
100                 optimization the user wants. If 0 is chosen, the circuit area
101                 will  be  improved. On the other hand, 4 will improve circuit
102                 delays. 2 is a medium value for optimization.
103
104       -x xsch_mode
105                 Generate a '.xsc' file. It is a color map  for  each  signals
106                 contained  in  output_file network. This file is used by xsch
107                 to view the netlist. By choosing level 0 or 1 for  xsch_mode,
108                 you  can  color respectively the critical path or all signals
109                 with delay graduation.
110
111       -o output_file
112                 Just another way to show explicitly the VST output file name.
113
114       -l lax_file
115                 Just another way to show explicitly the  LAX  parameter  file
116                 name.
117
118       -d debug_file
119                 Generates  a  VBE  debug  file. It comes from internal result
120                 algorithm. Users aren't concerned.
121
122

ENVIRONMENT VARIABLES

124       The following environment variables have to be set before using boog :
125
126
127       MBK_CATA_LIB gives the auxiliary paths  of  the  directories  of  input
128              files (behavioural description).
129
130
131       MBK_TARGET_LIB gives the path (single) of the directory of the selected
132              standard cell library.
133
134
135       MBK_OUT_LO gives the output format of the structural description.
136
137
138

EXAMPLE

140       You can call boog as follows :
141            boog alu alu
142
143
144
145