1VPASSERT(1) User Contributed Perl Documentation VPASSERT(1)
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6 vpassert - Preprocess Verilog code assertions
7
9 vpassert [ --help ] [ --date ] [ --quiet ] [ -y directories... ] [
10 files... ]
11
13 Vpassert will read the specified Verilog files and preprocess special
14 PLI assertions. The files are written to the directory named .vpassert
15 unless another name is given with -o. If a directory is passed, all
16 files in that directory will be preprocessed.
17
19 Standard VCS and GCC-like parameters are used to specify the files to
20 be preprocessed:
21 +libext+I<ext>+I<ext>... Specify extensions to be processed
23 -f I<file> Parse parameters in file
24 -v I<file> Parse the library file (I<file>)
25 -y I<dir> Parse all files in the directory (I<dir>)
26 -II<dir> Parse all files in the directory (I<dir>)
27 +incdir+I<dir> Parse all files in the directory (I<dir>)
28 To prevent recursion and allow reuse of the input.vc being passed to
30 the simulator, if the output directory is requested to be preprocessed,
31 that directory is simply ignored.
32 --allfiles
34 Preprocess and write out files that do not have any macros that
35 need expanding. By default, files that do not need processing are
36 not written out.
37 This option may speed up simulator compile times; the file will
39 always be found in the preprocessed directory, saving the compiler
40 from having to search a large number of -v directories to find it.
41 --axiom
43 Special Axiom ATHDL enables/disables added around unreachable code.
44 --call-error <function>
46 When $uerror (or $uassert etc.) wants to display a message, call
47 the specified function instead of $display and $stop.
48 --call-info <function>
50 When $uinfo wants to display a message, call the specified function
51 instead of $display.
52 --call-warn <function>
54 When $uwarn (or $uwarn_clk etc.) wants to display a message, call
55 the specified function instead of $display and $stop.
56 --date
58 Check file dates and sizes versus the last run of vpassert and
59 don't process if the given source file has not changed.
60 --exclude
62 Exclude processing any files which begin with the specified prefix.
63 --help
65 Displays this message and program version and exits.
66 --language
68 <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>
69 Set the language standard for the files. This determines which
70 tokens are signals versus keywords, such as the ever-common "do"
71 (data-out signal, versus a do-while loop keyword).
72 --minimum
74 Include `__message_minimum in the $uinfo test, so that by defining
75 __message_minimum=1 some uinfos may be optimized away at compile
76 time.
77 --noline
79 Do not emit `line directives. If not specified they will be used
80 under --language 1364-2001 and later.
81 --nopli
83 Delete all 'simple' PLI calls. PLI function calls inside
84 parenthesis will not be changed, and thus may still need to be
85 manually ifdef'ed out. Useful for reducing the amount of `ifdef's
86 required to feed non-PLI competent synthesis programs.
87 --nostop
89 By default, $error and $warn insert a $stop statement. With
90 --nostop, this is replaced by incrementing a variable, which may
91 then be used to conditionally halt simulation.
92 --o file
94 Use the given filename for output instead of the input name
95 .vpassert. If the name ends in a / it is used as a output
96 directory with the default name.
97 --quiet
99 Suppress messages about what files are being preprocessed.
100 --realintent
102 Special RealIntent enable/disables added around unreachable code.
103 --synthcov
105 When "ifdef SYNTHESIS" is seen, disable coverage. Resume on the
106 `else or `endif. This does NOT follow child defines, for example:
107 `ifdef SYNTHSIS
109 `define MYSYNTH
110 `endif
111 `ifdef MYSYNTH // This will not be coveraged-off
112 --timeformat-units units
114 If specified, include Verilog $timeformat calls before all
115 messages. Use the provided argument as the units. Units is in
116 powers of 10, so -9 indicates to use nanoseconds.
117 --timeformat-precision prec
119 When using --timeformat-units, use this as the precision value, the
120 number of digits after the decimal point. Defaults to zero.
121 --vericov
123 Special Vericov enable/disables added around unreachable code.
124 --verilator
126 Special Verilator translations enabled.
127 --version
129 Displays program version and exits.
130 --vcs
132 Special Synopsys VCS enables/disables added around unreachable
133 code.
134
136 These Verilog pseudo-pli calls are expanded:
137 /*vp_coverage_off*/
139 Disable coverage for all tools starting at this point. Does not
140 need to be on a unique line.
141 /*vp_coverage_on*/
143 Re-enable coverage after a vp_coverage_off. Does not need to be on
144 a unique line.
145 $uassert(case, "message", [vars...] )
147 Report a $uerror if the given case is FALSE. (Like assert() in C.)
148 $uassert_amone(sig, [sig...], "message", [vars...] )
150 Report a $uerror if more than one signal is asserted, or any are X.
151 (None asserted is ok.) The error message will include a binary
152 display of the signal values.
153 $uassert_info(case, "message", [vars...] )
155 Report a $uinfo if the given case is FALSE. (Like assert() in C.)
156 $uassert_onehot(sig, [sig...], "message", [vars...] )
158 Report a $uerror if other than one signal is asserted, or any are
159 X. The error message will include a binary display of the signal
160 values.
161 $uassert_req_ack(req_sig, ack_sig, [data_sig,...] )
163 Check for a single cycle request pulse, followed by a single cycle
164 acknowledgment pulse. Do not allow any of the data signals to
165 change between the request and acknowledgment.
166 $ucheck_ilevel(level )
168 Return true if the __message level is greater or equal to the given
169 level, and that global messages are turned on.
170 $ucover_clk(clock, label)
172 Similar to $uerror_clk, add a SystemVerilog assertion at the next
173 specified clock's edge, with the label specified. This allows cover
174 properties to be specified "inline" with normal RTL code.
175 $ucover_foreach_clk(clock, label, "msb:lsb", (... $ui ...))
177 Similar to $ucover_clk, however cover a range where $ui in the
178 expression is replaced with the range index.
179 Range is "msb:lsb" to indicate from msb downto lsb inclusive,
181 and/or a comma separated list of values.
182 Similar to:
184 for ($ui=msb; $ui>=lsb; $ui=$ui-1) begin
186 if (expression with $ui)
187 $ucover_clk(clock, label ## "_" ## bit)
188 end
189 However there's no way to form a label from a for loop (as
191 psudocoded with ## above), thus this macro.
192 $ui Loop index used inside $ucover_foreach_clk.
194 $uinfo(level, "message", [vars...] )
196 Report a informational message in standard form. End test if
197 warning limit exceeded.
198 $uerror("message", [vars...] )
200 Report a error message in standard form. End test if error limit
201 exceeded.
202 $uerror_clk(clock, "message", [vars...] )
204 Report a error message in standard form at the next clock edge. If
205 you place a $uerror etc in a combo logic block (always @*), event
206 based simulators may misfire the assertion due to glitches.
207 $uerror_clk fixes this by instead creating a temporary signal and
208 then moving the assert itself to a new clocked block at the
209 specified edge. Note any variables printed will be the values at
210 the time of the next clock edge, which may differ from the value
211 where the $uerror_clk is assigned.
212 $uwarn("message", [vars...] )
214 Report a warning message in standard form.
215 $uwarn_clk(clock "message", [vars...] )
217 Report a warning message in standard form at the next clock edge.
218 See $uerror_clk.
219
221 Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
222 EDA software tool suite. The latest version is available from CPAN and
223 from <https://www.veripool.org/verilog-perl>.
224 Copyright 2000-2022 by Wilson Snyder. This package is free software;
226 you can redistribute it and/or modify it under the terms of either the
227 GNU Lesser General Public License Version 3 or the Perl Artistic
228 License Version 2.0.
229
231 Wilson Snyder <wsnyder@wsnyder.org>, Duane Galbi
232 <duane.galbi@conexant.com>
233
235 Verilog-Perl, Verilog::Parser, Verilog::Pli
236perl v5.38.0 2023-07-21 VPASSERT(1)