1YASM_ARCH(7) Yasm Supported Architectures YASM_ARCH(7)
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6 yasm_arch - Yasm Supported Target Architectures
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9 yasm -a arch [-m machine] ...
10
12 The standard Yasm distribution includes a number of modules for
13 different target architectures. Each target architecture can support
14 one or more machine architectures.
15 The architecture and machine are selected on the yasm(1) command line
17 by use of the -a arch and -m machine command line options,
18 respectively.
19 The machine architecture may also automatically be selected by certain
21 object formats. For example, the “elf32” object format selects the
22 “x86” machine architecture by default, while the “elf64” object format
23 selects the “amd64” machine architecture by default.
24
26 The “x86” architecture supports the IA-32 instruction set and
27 derivatives and the AMD64 instruction set. It consists of two machines:
28 “x86” (for the IA-32 and derivatives) and “amd64” (for the AMD64 and
29 derivatives). The default machine for the “x86” architecture is the
30 “x86” machine.
31 BITS Setting
33 The x86 architecture BITS setting specifies to Yasm the processor mode
34 in which the generated code is intended to execute. x86 processors can
35 run in three different major execution modes: 16-bit, 32-bit, and on
36 AMD64-supporting processors, 64-bit. As the x86 instruction set
37 contains portions whose function is execution-mode dependent (such as
38 operand-size and address-size override prefixes), Yasm cannot assemble
39 x86 instructions correctly unless it is told by the user in what
40 processor mode the code will execute.
41 The BITS setting can be changed in a variety of ways. When using the
43 NASM-compatible parser, the BITS setting can be changed directly via
44 the use of the BITS xx assembler directive. The default BITS setting is
45 determined by the object format in use.
46 BITS 64 Extensions
48 The AMD64 architecture is a new 64-bit architecture developed by AMD,
49 based on the 32-bit x86 architecture. It extends the original x86
50 architecture by doubling the number of general purpose and SIMD
51 registers, extending the arithmetic operations and address space to 64
52 bits, as well as other features.
53 Recently, Intel has introduced an essentially identical version of
55 AMD64 called EM64T.
56 When an AMD64-supporting processor is executing in 64-bit mode, a
58 number of additional extensions are available, including extra general
59 purpose registers, extra SSE2 registers, and RIP-relative addressing.
60 Yasm extends the base NASM syntax to support AMD64 as follows. To
62 enable assembly of instructions for the 64-bit mode of AMD64
63 processors, use the directive BITS 64. As with NASM's BITS directive,
64 this does not change the format of the output object file to 64 bits;
65 it only changes the assembler mode to assume that the instructions
66 being assembled will be run in 64-bit mode. To specify an AMD64 object
67 file, use -m amd64 on the Yasm command line, or explicitly target a
68 64-bit object format such as -f win64 or -f elf64.
69 Register Changes
71 The additional 64-bit general purpose registers are named
72 r8-r15. There are also 8-bit (rXb), 16-bit (rXw), and 32-bit
73 (rXd) subregisters that map to the least significant 8, 16, or
74 32 bits of the 64-bit register. The original 8 general purpose
75 registers have also been extended to 64-bits: eax, edx, ecx,
76 ebx, esi, edi, esp, and ebp have new 64-bit versions called rax,
77 rdx, rcx, rbx, rsi, rdi, rsp, and rbp respectively. The old
78 32-bit registers map to the least significant bits of the new
79 64-bit registers.
80 New 8-bit registers are also available that map to the 8 least
82 significant bits of rsi, rdi, rsp, and rbp. These are called
83 sil, dil, spl, and bpl respectively. Unfortunately, due to the
84 way instructions are encoded, these new 8-bit registers are
85 encoded the same as the old 8-bit registers ah, dh, ch, and bh.
86 The processor tells which is being used by the presence of the
87 new REX prefix that is used to specify the other extended
88 registers. This means it is illegal to mix the use of ah, dh,
89 ch, and bh with an instruction that requires the REX prefix for
90 other reasons. For instance:
91 add ah, [r10]
93 (NASM syntax) is not a legal instruction because the use of r10
95 requires a REX prefix, making it impossible to use ah.
96 In 64-bit mode, an additional 8 SSE2 registers are also
98 available. These are named xmm8-xmm15.
99 64 Bit Instructions
101 By default, most operations in 64-bit mode remain 32-bit;
102 operations that are 64-bit usually require a REX prefix (one bit
103 in the REX prefix determines whether an operation is 64-bit or
104 32-bit). Thus, essentially all 32-bit instructions have a 64-bit
105 version, and the 64-bit versions of instructions can use
106 extended registers “for free” (as the REX prefix is already
107 present). Examples in NASM syntax:
108 mov eax, 1 ; 32-bit instruction
110 mov rcx, 1 ; 64-bit instruction
112 Instructions that modify the stack (push, pop, call, ret, enter,
114 and leave) are implicitly 64-bit. Their 32-bit counterparts are
115 not available, but their 16-bit counterparts are. Examples in
116 NASM syntax:
117 push eax ; illegal instruction
119 push rbx ; 1-byte instruction
121 push r11 ; 2-byte instruction with REX prefix
123 Implicit Zero Extension
125 Results of 32-bit operations are implicitly zero-extended to the
126 upper 32 bits of the corresponding 64-bit register. 16 and 8 bit
127 operations, on the other hand, do not affect upper bits of the
128 register (just as in 32-bit and 16-bit modes). This can be used
129 to generate smaller code in some instances. Examples in NASM
130 syntax:
131 mov ecx, 1 ; 1 byte shorter than mov rcx, 1
133 and edx, 3 ; equivalent to and rdx, 3
135 Immediates
137 For most instructions in 64-bit mode, immediate values remain 32
138 bits; their value is sign-extended into the upper 32 bits of the
139 target register prior to being used. The exception is the mov
140 instruction, which can take a 64-bit immediate when the
141 destination is a 64-bit register. Examples in NASM syntax:
142 add rax, 1 ; optimized down to signed 8-bit
144 add rax, dword 1 ; force size to 32-bit
146 add rax, 0xffffffff ; sign-extended 32-bit
148 add rax, -1 ; same as above
150 add rax, 0xffffffffffffffff ; truncated to 32-bit (warning)
152 mov eax, 1 ; 5 byte
154 mov rax, 1 ; 5 byte (optimized to signed 32-bit)
156 mov rax, qword 1 ; 10 byte (forced 64-bit)
158 mov rbx, 0x1234567890abcdef ; 10 byte
160 mov rcx, 0xffffffff ; 10 byte (does not fit in signed 32-bit)
162 mov ecx, -1 ; 5 byte, equivalent to above
164 mov rcx, sym ; 5 byte, 32-bit size default for symbols
166 mov rcx, qword sym ; 10 byte, override default size
168 Displacements
170 Just like immediates, displacements, for the most part, remain
171 32 bits and are sign extended prior to use. Again, the exception
172 is one restricted form of the mov instruction: between the
173 al/ax/eax/rax register and a 64-bit absolute address (no
174 registers allowed in the effective address). In NASM syntax, use
175 of the 64-bit absolute form requires [qword]. Examples in NASM
176 syntax:
177 mov eax, [1] ; 32 bit, with sign extension
179 mov al, [rax-1] ; 32 bit, with sign extension
181 mov al, [qword 0x1122334455667788] ; 64-bit absolute
183 mov al, [0x1122334455667788] ; truncated to 32-bit (warning)
185 RIP Relative Addressing
187 In 64-bit mode, a new form of effective addressing is available
188 to make it easier to write position-independent code. Any memory
189 reference may be made RIP relative (RIP is the instruction
190 pointer register, which contains the address of the location
191 immediately following the current instruction).
192 In NASM syntax, there are two ways to specify RIP-relative
194 addressing:
195 mov dword [rip+10], 1
197 stores the value 1 ten bytes after the end of the instruction.
199 10 can also be a symbolic constant, and will be treated the same
200 way. On the other hand,
201 mov dword [symb wrt rip], 1
203 stores the value 1 into the address of symbol symb. This is
205 distinctly different than the behavior of:
206 mov dword [symb+rip], 1
208 which takes the address of the end of the instruction, adds the
210 address of symb to it, then stores the value 1 there. If symb is
211 a variable, this will not store the value 1 into the symb
212 variable!
213
215 The “lc3b” architecture supports the LC-3b ISA as used in the ECE 312
216 (now ECE 411) course at the University of Illinois, Urbana-Champaign,
217 as well as other university courses. See
218 http://courses.ece.uiuc.edu/ece411/ for more details and example code.
219 The “lc3b” architecture consists of only one machine: “lc3b”.
220
222 yasm(1)
223
225 When using the “x86” architecture, it is overly easy to generate AMD64
226 code (using the BITS 64 directive) and generate a 32-bit object file
227 (by failing to specify -m amd64 on the command line or selecting a
228 64-bit object format). Similarly, specifying -m amd64 does not default
229 the BITS setting to 64. An easy way to avoid this is by directly
230 specifying a 64-bit object format such as -f elf64.
231
233 Peter Johnson <peter@tortall.net>
234 Author.
235
237 Copyright © 2004, 2005, 2006 Peter Johnson
238Yasm October 2006 YASM_ARCH(7)